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71M6521BE-IGTR/F 参数 Datasheet PDF下载

71M6521BE-IGTR/F图片预览
型号: 71M6521BE-IGTR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 97 页 / 1586 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6521BE  
Energy Meter IC  
DATA SHEET  
JANUARY 2008  
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used  
to select the appropriate mode.  
Timer/Counter Mode Control register (TMOD):  
MSB  
GATE  
LSB  
M0  
C/T  
M1  
M0  
GATE  
C/T  
M1  
Timer 1  
Timer 0  
Table 20: The TMOD Register  
Bits TR1 (TCON.6) and TR0 (TCON.4) in the TCON register (see Table 18 and Table 19) start their associated timers when set.  
Bit  
Symbol  
Function  
TMOD.7  
TMOD.3  
Gate  
If set, enables external gate control (pin int0 or int1 for Counter 0 or 1,  
respectively). When int0 or int1 is high, and TRX bit is set (see TCON register), a  
counter is incremented every falling edge on T0 or T1 input pin  
TMOD.6  
TMOD.2  
C/T  
M1  
M0  
Selects Timer or Counter operation. When set to 1, a Counter operation is  
performed. When cleared to 0, the corresponding register will function as a Timer.  
TMOD.5  
TMOD.1  
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD  
description.  
TMOD.4  
TMOD.0  
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD  
description.  
Table 21: TMOD Register Bit Description  
M1  
M0  
Mode  
Mode 0  
Function  
0
0
13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the  
remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1,  
respectively). The 3 high order bits of TL0 and TL1 are held at zero.  
0
1
1
0
Mode 1  
Mode 2  
16-bit Counter/Timer.  
8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1,  
while TL0 or TL1 is incremented every machine cycle. When TL(x) overflows,  
a value from TH(x) is copied to TL(x).  
1
1
Mode 3  
If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0  
bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters.  
Table 22: Timers/Counters Mode Description  
Note:  
In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while  
TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow.  
Page: 26 of 97  
© 2005-2008 TERIDIAN Semiconductor Corporation  
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