71M6515H
Energy Meter IC
DATA SHEET
MARCH 2008
Bits 23-22: These two bits (IMAGE) select the code to be used by the CE. The CE can be operated in standard mode
when using CTs and/or shunt resistor sensors or in Rogowski mode when using Rogowski coil sensors. In order to switch
the operation mode, the CE has to be disabled first by clearing the CE_EN bit.
Bit 23
IMAGE 1
Bit 22
IMAGE 0
IMAGE
CE Code Selected
0
0
1
1
0
1
0
1
0
1
2
3
Standard (CT/shunt)
Rogowski coil
Standard (CT/shunt)
Standard (CT/shunt)
Bit 24: This bit (RESET), when reset, forces all internal states of the 71M6515H to their power-up default.
Bits 26-25: These two bits (PULSE_SLOW, PULSE_FAST) modify the speed of the pulse generator. PULSE_SLOW and
PULSE_FAST determine the factor X in the equation used for Kh as shown in the table below.
PULSE_SLOW
PULSE_FAST
X
1.5*22 = 6
1.5*26 = 96
1.5*2-4 = 0.09375
1.5
0
0
1
0
1
0
1 (default)
1 (default)
PULSE_SLOW and PULSE_FAST will affect the operation of all four pulse outputs. See the Pulse Generation section for
details.
Bits 29-27: These three bits (IA_8X, IB_8X, IC_8X) apply an additional gain of 8 to the IA, IB, and IC channels when set to
1. This is a useful tool when very small signals are encountered, as is the case when using current shunt resistors with very
low resistance while operating at low currents. Care must be taken to avoid clipping. If the input to the meter exceeds
IMAX/8, clipping will occur. These bits should normally be zero, unless additional gain following the ADC stage is needed.
Bit 30: This bit (DEFAULT_PPM) defines the source of temperature compensation. When DEFAULT_PPM is 1, the
71M6515H will automatically apply compensation coefficients derived from the stored VREF temperature characteristics to
the PPMC and PPMC2 registers. When DEFAULT_PPM is zero, the host is allowed to write its own values to the PPMC and
PPMC2 registers.
STATUS (0x14)
The four bytes in this register reflect the status of the various measurement functions of the 71M6515H. This register is
read only. When a bit in the STMASK register is set, an interrupt (IRQZ) is generated as soon as the corresponding bit in
the STATUS register is set.
Bit 0: This bit (BOOTUP) signals a request from the 71M6515H to the host to be initialized.
Bit 1: This bit (SAGA ), when set, indicates that the voltage applied to phase A has sagged below SAGTHR. See the for SAG
register for a detailed description.
Bit 2: This bit (SAGB), when set, indicates that the voltage applied to phase B has sagged below SAGTHR.
Bit 3: This bit (SAGC), when set, indicates that the voltage applied to phase C has sagged below SAGTHR.
Bit 4: This bit (F0) follows the polarity of the input voltage selected with the F_SELECT bits in the CONFIG register. It
represents a smoothed, filtered and squared copy of the fundamental waveform.
Bit 5: This bit (MAXV), when set, indicates that a voltage greater than the voltage limit defined in the VI_PTHRESHOLD
register had been detected in the previous accumulation interval.
Bit 6: This bit (MAXI), when set, indicates that a current greater than the current limit defined in the VI_PTHRESHOLD
register had been detected in the previous accumulation interval.
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