71M6515H
Energy Meter IC
DATA SHEET
MARCH 2008
Bits 13-8: These six bits (SUM_CYCLES) define the length of the accumulation interval τ per the formula:
SUM _ CYCLES ⋅ 42
τ =
2520.6
Allowed values are 24 (400ms) through 60 (1000ms), unless the post-processor is disabled. Bit 8 is the LSB.
It is important to note that the length of the accumulation interval, as determined by SUM_CYCLES, is not an exact multiple
of 1000ms. For example, if SUM_CYCLES = 60, the resulting accumulation interval is:
60⋅ 42
32768Hz
13
2520
τ =
=
= 999.75ms
2520.62Hz
This means that accurate time measurements should be based on the RTC, not the accumulation interval.
Bit 14: This bit (CKOUT_DISB) disables the CKOUT pin when set. The CKOUT pin can be used for diagnostics. For EMC
compliance and power saving reasons, CKOUT_DISB should always be set.
Bit 15: This bit (ADC_DIS) disables the ADC when set, e.g. to save power. Of course, no metering or measuring can be
performed with the ADC disabled.
Bits 18-16: These three bits (TMUX) select the source for the TMUX diagnostic output pin. For EMC compliance and
power saving reasons, TMUX should be zero (default) if unused.
Bit 18
TMUX2
Bit 17
TMUX1
Bit 16
TMUX0
TMUX
Signal Selected for the TMUX Pin
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
GND
MUX_SYNC
RTM
RTC Output
CE_BUSY
XFER_BUSY
VX_OK (Comparator Output)
V3P3/2 =1.5V internal analog voltage
Bits 20-19: These two bits (F_SELECT) select the phase that is to be used for frequency measurement. The frequency will
be shown in bits 31-16 of the FREQ_DELTA_T register (and as bit 4 of the STATUS word – in this form as a digitized zero
crossing signal).
Bit 20
Bit 19
Phase
F_SELECT
F_SELECT1 F_SELECT0
Selected
Phase A
Phase B
Phase C
Not allowed
0
0
1
1
0
1
0
1
0
1
2
3
Since the signal at the input selected with F_SELECT is used to synchronize filters and other processing stages in the CE,
accuracy for most measurements will be reduced if no voltage is present at the selected phase input. Accuracy can be
established by selecting the phase that carries a stable signal (A, B, or C).
Bit 21: This bit (CE_ONLY) disables the post-processor when set to 1. When the post-processor is disabled, the time-
intensive computations of IPHASE, IRMS, VAh and VRMS are not performed, and therefore smaller accumulation times
(SUM_CYCLES < 24) are permitted. In this case, the host is responsible for calculating IPHASE, IRMS, VAh and VRMS.
Page: 36 of 57
© 2005-2008 TERIDIAN Semiconductor Corporation
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