TSC87C52
Clock Waveforms
STATE4
STATE5
P1 P2
STATE6
P1 P2
STATE1
STATE2
P1 P2
STATE3
P1 P2
STATE4
P1 P2
STATE5
P1 P2
INTERNAL
CLOCK
P1
P2
P1
P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
DATA
PCL OUT
DATA
PCL OUT
DATA
PCL OUT
SAMPLED
SAMPLED
SAMPLED
FLOAT
FLOAT
FLOAT
P2 (EXT)
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0
P2
DPL OR Rt OUT
DATA
SAMPLED
FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRITE CYCLE
WR
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
P0
P2
DPL OR Rt OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION
MOV PORT SRC
OLD DATA
NEW DATA
P0 PINS SAMPLED
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA=25_C fully loaded) RD
and WR propagation delays are approximately 50ns. The other signals are typically 85ns. Propagation delays are
incorporated in the AC specifications.
MATRA MHS
Rev. C – 10 Sept 1997
23
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
