TSC87C52
External Data Memory Characteristics
0 to 12MHz
Symbol
Parameter
Units
Max
Min
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
TRLAZ
TWHLH
RD Pulse Width
6TCLCL–100
6TCLCL–100
ns
ns
WR Pulse Width
RD to Valid Data In
5TCLCL–165
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold After RD
0
Data Float After RD
2TCLCL–60
8TCLCL–150
9TCLCL–165
3TCLCL+50
ALE to Valid Data In
Address to Valid Data In
ALE to WR or RD
3TCLCL–50
4TCLCL–130
TCLCL–50
Address to WR or RD
Data Valid to WR Transition
Data set–up to WR High
Data Hold After WR
RD Low to Address Float
RD or WR High to ALE high
7TCLCL–150
TCLCL–50
0
TCLCL–40
TCLCL+40
External Data Memory Write Cycle
TWHLH
ALE
PSEN
WR
TLLWL
TWLWH
TQVWX
TWHQX
TLLAX
TQVWH
PORT 0
PORT 2
A0–A7
TAVWL
DATA OUT
ADDRESS
OR SFR–P2
ADDRESS A8–A15 OR SFR P2
MATRA MHS
Rev. C – 10 Sept 1997
19
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
