TSC87C52
External Data Memory Read Cycle
TWHLH
TLLDV
ALE
PSEN
RD
TLLWL
TRLRH
TRHDZ
TAVDV
TLLAX
A0–A7
TAVWL
TRHDX
DATA IN
PORT 0
PORT 2
TRLAZ
ADDRESS A8–A15 OR SFR P2
ADDRESS
OR SFR–P2
Serial Port Timing – Shift Register Mode
0 to 12MHz
Symbol
Parameter
Units
Min
Max
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Serial port clock cycle time
12TCLCL
ns
ns
ns
ns
ns
Output data set–up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10TCLCL–133
2TCLCL–117
0
10TCLCL–133
Shift Register Timing Waveforms
0
1
2
3
4
5
6
7
8
INSTRUCTION
ALE
TXLXL
CLOCK
TXHQX
1
TQVXH
0
2
3
4
5
6
7
OUTPUT DATA
TXHDX
SET TI
TXHDV
WRITE to SBUF
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
MATRA MHS
Rev. C – 10 Sept 1997
20
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
