TS80C52X2
8-bit CMOS Microcontroller 0-60 MHz
1. Description
TEMIC TS80C52X2 is high performance CMOS ROM, The fully static design of the TS80C52X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
OTP, EPROM and ROMless versions of the 80C51
CMOS single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the TEMIC
80C51 with extended ROM/EPROM capacity (8
Kbytes), 256 bytes of internal RAM, a 6-source , 4-level
interrupt system, an on-chip oscilator and three timer/
counters.
The TS80C52X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
In addition, the TS80C52X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
2. Features
● 80C52 Compatible
● Interrupt Structure with
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8051 pin and instruction compatible
Four 8-bit I/O ports
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6 Interrupt sources,
4 level priority interrupt system
Three 16-bit timer/counters
256 bytes scratchpad RAM
● Full duplex Enhanced UART
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Framing error detection
Automatic address recognition
● High-Speed Architecture
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40 MHz @ 5V, 30MHz @ 3V
● Low EMI (inhibit ALE)
● Power Control modes
X2 Speed Improvement capability (6 clocks/
machine cycle)
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Idle mode
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
Power-down mode
Power-off Flag
● Dual Data Pointer
● Once mode (On-chip Emulation)
● Power supply: 4.5-5V, 2.7-5.5V
● On-chip ROM/EPROM (8K-bytes)
● Programmable Clock Out and Up/Down Timer/
● Temperature ranges: Commercial (0 to 70oC) and
Counter 2
Industrial (-40 to 85oC)
● Asynchronous port reset
● Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1
(13.9 footprint), CQPJ44 (window), CDIL40
(window)
Rev. B - Jan. 25, 1999
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Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
