MATRA MHS
L 67201/L 67202
single word to be read after one word has been written to In the write flow-through mode (figure 18), the FIFO
an empty FIFO stack. The data is enabled on the bus at stack allows a single word of data to be written
(tWEF + tA) ns after the leading edge of W which is immediately after a single word of data has been read
known as the first write edge and remains on the bus until from a full FIFO stack. The R line causes the FF to be
the R line is raised from low to high, after which the bus reset, but the W line, being low, causes it to be set again
will go into a three-state mode after tRHZ ns. The EF line in anticipation of a new data word. The new word is
will show a pulse indicating temporary reset and then will loaded into the FIFO stack on the leading edge of W. The
be set. In the interval in which R is low, more words may W line must be toggled when FF is not set in order to write
be written to the FIFO stack (the subsequent writes after new data into the FIFO stack and to increment the write
the first write edge will reset the Empty Flag) ; however, pointer.
the same word (written on the first write edge) presented
to the output bus as the read pointer will not be
incremented if R is low. On toggling R, the remaining
words written to the FIFO will appear on the output bus
in accordance with the read cycle timings.
Figure 4. Block Diagram of 1536 × 9 / 3072 × 9 FIFO Memory (Depth expansion).
XO
W
R
FF
9
EF
FL
6
9
L
9
67201/202
Q
V
CC
FULL
EMPTY
FF
9
EF
FL
L
67201/202
EF
FL
FF
9
L
67201/202
RS
XI
Figure 5. Compound FIFO Expansion.
Q
0
– Q
Q
Q
– Q
– Q
Q
Q
– Q
– Q
8
9
17
(N–8)
N
Q
0
– Q
8
9
17
(N–8)
N
L 67201/202
L 67201/202
L 67201/202
R . W . RS
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
I
0
– I
8
I
9
– I
17
I
– I
N
(N–8)
I
0
– I
8
I
9
– I
17
I – I
(N–8) N
Notes : 6. For depth expansion block see section on Depth Expansion and Figure 4.
7. For Flag detection see section on Width Expansion and Figure 3.
Rev. C (10/11/95)
7
TEMIC [ TEMIC SEMICONDUCTORS ]
