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A4J-L67202L-55 参数 Datasheet PDF下载

A4J-L67202L-55图片预览
型号: A4J-L67202L-55
PDF下载: 下载PDF文件 查看货源
内容描述: [FIFO, 1KX9, 55ns, Asynchronous, CMOS, LCC-32]
分类和应用: 先进先出芯片
文件页数/大小: 16 页 / 146 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
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L 67201/L 67202  
MATRA MHS  
Table 1 : Reset and retransmit  
Single Device Configuration/Width Expansion Mode  
INPUTS  
INTERNAL STATUS  
Read Pointer Write Pointer  
OUTPUTS  
MODE  
RS  
0
RT  
X
XI  
0
EF  
0
FF  
1
HF  
1
Reset  
Location Zero  
Location Zero  
Location Zero  
Unchanged  
Retransmit  
Read/Write  
1
0
0
X
X
X
(4)  
(4)  
1
1
0
Increment  
Increment  
X
X
X
Note : 4. Pointer will increment if flag is high.  
Table 2 : Reset and First Load Truth Table  
Depth Expansion/Compound Expansion Mode  
INPUTS  
INTERNAL STATUS  
OUTPUTS  
MODE  
RS  
0
FL  
0
XI  
(5)  
(5)  
(5)  
Read Pointer  
Write Pointer  
Location Zero  
Location Zero  
X
EF  
FF  
1
Reset First Device  
Reset All Other Devices  
Read/Write  
Location Zero  
Location Zero  
X
0
0
0
1
1
1
X
X
X
Note : 5. XI is connected to XO of previous device.  
See fig. 5.  
Depth Expansion (Daisy Chain) Mode  
Compound Expansion Module  
It is quite simple to apply the two expansion techniques  
described above together to create large FIFO arrays (see  
figure 5).  
The L 67201/202 can be easily adapted for applications  
which require more than 512/1024 words. Figure 4  
demonstrates Depth Expansion using three L 67201/202.  
Any depth can be achieved by adding additional  
67201/202.  
Bidirectional Mode  
The L 67201/202 operate in the Depth Expansion  
configuration if the following conditions are met :  
Applications which require data buffering between two  
systems (each system being capable of Read and Write  
operations) can be created by coupling L 67201/202 as  
shown in figure 6. Care must be taken to ensure that the  
appropriate flag is monitored by each system (i.e. FF is  
monitored on the device on which W is in use ; EF is  
monitored on the device on which R is in use). Both Depth  
Expansion and Width Expansion may be used in this  
mode.  
1. The first device must be designated by connecting the  
First Load (FL) control input to ground.  
2. All other devices must have FL in the high state.  
3. The Expansion Out (XO) pin of each device must be  
connected to the Expansion In (XI) pin of the next  
device. See figure 4.  
4. External logic is needed to generate a composite Full  
Flag (FF) and Empty Flag (EF). This requires that all  
EF’s and all FFs be ØRed (i.e. all must be set to  
generate the correct composite FF or EF). See figure 4.  
Data Flow - Through Modes  
Two types of flow-through modes are permitted : a read  
5. The Retransmit (RT) function and Half-Full Flag (HF) flow-through and a write flow-through mode. In the read  
are not available in the Depth Expansion Mode. flow-through mode (figure 17) the FIFO stack allows a  
6
Rev. C (10/11/95)  
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