TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
APPLICATION INFORMATION: HARDWARE
Typical Hardware Application
A typical hardware application circuit is shown in Figure 10. A 1-μF low-ESR decoupling capacitor should be
placed as close as possible to the V pin.
DD
V
V
BUS
DD
V
DD
R
P
R
P
R
PI
1 mF
TSL2571
INT
SCL
SDA
GND
Figure 10. Typical Application Hardware Circuit
2
2
V
BUS
in Figure 10 refers to the I C bus voltage, which is either V or 1.8 V. Be sure to apply the specified I C
DD
bus voltage shown in the Available Options table for the specific device being used.
2
The I C signals and the Interrupt are open-drain outputs and require pull-up resistors. The pull-up resistor (R )
P
2
2
value is a function of the I C bus speed, the I C bus voltage, and the capacitive load. The TAOS EVM running
at 400 kbps, uses 1.5-kΩ resistors. A 10-kΩ pull-up resistor (R ) can be used for the interrupt line.
PI
PCB Pad Layout
Suggested PCB pad layout guidelines for the Dual Flat No-Lead (FN) surface mount package are shown in
Figure 11.
2500
Note: Pads can be
extended further if hand
soldering is needed.
1000
1000
400
650
650
1700
400
NOTES: A. All linear dimensions are in micrometers.
B. This drawing is subject to change without notice.
Figure 11. Suggested FN Package PCB Layout
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
r
r
www.taosinc.com
19
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
