TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066J − MAY 2007
Table 7. Interrupt Threshold Register
REGISTER
ADDRESS
BITS
7:0
DESCRIPTION
THRESHLOWLOW
THRESHLOWHIGH
THRESHHIGHLOW
THRESHHIGHHIGH
2h
3h
4h
5h
ADC channel 0 lower byte of the low threshold
ADC channel 0 upper byte of the low threshold
ADC channel 0 lower byte of the high threshold
ADC channel 0 upper byte of the high threshold
7:0
7:0
7:0
NOTE: Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the Send Byte protocol should
not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted as the
COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desired.
The Write Word protocol should be used to write byte-paired registers. For example, the THRESHLOWLOW and THRESHLOWHIGH
registers (as well as the THRESHHIGHLOW and THRESHHIGHHIGH registers) can be written together to set the 16-bit ADC value in
a single transaction.
Interrupt Control Register (6h)
The INTERRUPT register controls the extensive interrupt capabilities of the TSL256x. The TSL256x permits
both SMB-Alert style interrupts as well as traditional level-style interrupts. The interrupt persist bit field
(PERSIST) provides control over when interrupts occur. A value of 0 causes an interrupt to occur after every
integration cycle regardless of the threshold settings. A value of 1 results in an interrupt after one integration
time period outside the threshold window. A value of N (where N is 2 through15) results in an interrupt only if
the value remains outside the threshold window for N consecutive integration cycles. For example, if N is equal
to 10 and the integration time is 402 ms, then the total time is approximately 4 seconds.
When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value
outside of the programmed threshold window. The interrupt is active-low and remains asserted until cleared by
writing the COMMAND register with the CLEAR bit set.
In SMBAlert mode, the interrupt is similar to the traditional level style and the interrupt line is asserted low. To
clear the interrupt, the host responds to the SMBAlert by performing a modified Receive Byte operation, in which
the Alert Response Address (ARA) is placed in the slave address field, and the TSL256x that generated the
interrupt responds by returning its own address in the seven most significant bits of the receive data byte. If more
than one device connected on the bus has pulled the SMBAlert line low, the highest priority (lowest address)
device will win communication rights via standard arbitration during the slave address transfer. If the device
loses this arbitration, the interrupt will not be cleared. The Alert Response Address is 0Ch.
When INTR = 11, the interrupt is generated immediately following the SMBus write operation. Operation then
behaves in an SMBAlert mode, and the software set interrupt may be cleared by an SMBAlert cycle.
NOTE: Interrupts are based on the value of Channel 0 only.
Table 8. Interrupt Control Register
7
Resv
0
6
Resv
0
5
4
3
2
1
0
0
0
INTERRUPT
6h
INTR
PERSIST
Reset Value:
0
0
0
0
FIELD
Resv
BITS
7:6
DESCRIPTION
Reserved. Write as 0.
INTR Control Select. This field determines mode of interrupt logic according to Table 9, below.
Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 10, below.
INTR
5:4
PERSIST
3:0
Copyright E 2007, TAOS Inc.
The LUMENOLOGY r Company
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