TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066J − MAY 2007
ADC Channel Data Registers (Ch − Fh)
The ADC channel data are expressed as 16-bit values spread across two registers. The ADC channel 0 data
registers, DATA0LOW and DATA0HIGH provide the lower and upper bytes, respectively, of the ADC value of
channel 0. Registers DATA1LOW and DATA1HIGH provide the lower and upper bytes, respectively, of the ADC
value of channel 1. All channel data registers are read-only and default to 00h on power up.
Table 12. ADC Channel Data Registers
REGISTER
DATA0LOW
DATA0HIGH
DATA1LOW
DATA1HIGH
ADDRESS
BITS
7:0
DESCRIPTION
ADC channel 0 lower byte
Ch
Dh
Eh
Fh
7:0
ADC channel 0 upper byte
ADC channel 1 lower byte
ADC channel 1 upper byte
7:0
7:0
The upper byte data registers can only be read following a read to the corresponding lower byte register. When
the lower byte register is read, the upper eight bits are strobed into a shadow register, which is read by a
subsequent read to the upper byte. The upper register will read the correct value even if additional ADC
integration cycles end between the reading of the lower and upper registers.
NOTE: The Read Word protocol can be used to read byte-paired registers. For example, the DATA0LOW and DATA0HIGH registers (as well as
the DATA1LOW and DATA1HIGH registers) may be read together to obtain the 16-bit ADC value in a single transaction
Copyright E 2007, TAOS Inc.
The LUMENOLOGY r Company
r
r
www.taosinc.com
17
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
