TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066J − MAY 2007
1
7
1
1
8
1
8
1
8
1
...
S
Slave Address
Wr
A
Command Code
A
Byte Count = N
A
Data Byte 1
A
8
1
8
1
1
...
Data Byte 2
A
Data Byte N
A
P
2
Figure 14. SMBus Block Write or I C Write Protocols
2
NOTE: The I C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates a
Stop condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
1
7
1
1
8
1
1
7
1
1
8
1
...
S
Slave Address
Wr
A
Command Code
A
Sr Slave Address Rd
A
Byte Count = N
A
8
1
8
1
8
1
1
...
Data Byte 1
A
Data Byte 2
A
Data Byte N
A
1
P
2
Figure 15. SMBus Block Read or I C Read (Combined Format) Protocols
2
NOTE: The I C read protocol does not use the Byte Count packet, and the Master will continue receiving Data Bytes until the Master initiates
a Stop Condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
Register Set
The TSL256x is controlled and monitored by sixteen registers (three are reserved) and a command register
accessed through the serial interface. These registers provide for a variety of control functions and can be read
to determine results of the ADC conversions. The register set is summarized in Table 2.
Table 2. Register Address
ADDRESS
−−
RESISTER NAME
COMMAND
REGISTER FUNCTION
Specifies register address
0h
CONTROL
Control of basic functions
1h
TIMING
Integration time/gain control
Low byte of low interrupt threshold
2h
THRESHLOWLOW
3h
THRESHLOWHIGH High byte of low interrupt threshold
THRESHHIGHLOW Low byte of high interrupt threshold
THRESHHIGHHIGH High byte of high interrupt threshold
4h
5h
6h
INTERRUPT
−−
Interrupt control
7h
Reserved
8h
CRC
Factory test — not a user register
Reserved
9h
−−
Ah
ID
Part number/ Rev ID
Reserved
Bh
−−
Ch
Dh
Eh
DATA0LOW
DATA0HIGH
DATA1LOW
DATA1HIGH
Low byte of ADC channel 0
High byte of ADC channel 0
Low byte of ADC channel 1
High byte of ADC channel 1
Fh
The mechanics of accessing a specific register depends on the specific SMB protocol used. Refer to the section
on SMBus protocols. In general, the COMMAND register is written first to specify the specific control/status
register for following read/write operations.
Copyright E 2007, TAOS Inc.
The LUMENOLOGY r Company
r
r
12
www.taosinc.com
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
