TSL2301
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOGĆTOĆDIGITAL CONVERTER
TAOS007 – JULY 2000
Table 1. Gain Settings and Results
GAIN CODE
RELATIVE GAIN
1.00
% INCREASE
GAIN CODE
RELATIVE GAIN
1.52
% INCREASE
3.23
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1.02
2.17
2.22
2.27
2.33
2.38
2.44
2.50
2.56
2.63
2.70
2.78
2.86
2.94
3.03
3.13
1.57
3.33
2
1.05
1.62
3.45
3
1.07
1.68
3.57
4
1.09
1.74
3.70
5
1.12
1.81
3.85
6
1.15
1.88
4.00
7
1.18
1.96
4.17
8
1.21
2.05
4.35
9
1.24
2.14
4.55
10
11
12
13
14
15
1.27
2.24
4.76
1.31
2.35
5.00
1.34
2.48
5.26
1.38
2.61
5.56
1.43
2.77
5.88
1.47
2.94
6.25
Register address map
The TSL2301 contains seven registers (Table 2). Three registers control the gain of the analog-to-digital
converters (ADCs). Three other registers allow the offset of the system to be corrected. Together the gain and
offset registers are used to maximize the achievable dynamic range. The last register is a mode register that
selects both device cascade options and production test options. Note that device cascade options do not apply
to the 8-pin packaged device.
Table 2. Register Address Map
ADDRESS REGISTER DESCRIPTION REGISTER WIDTH
0
1
Pixels 0–33 Offset
Pixels 0–33 Gain
Pixels 34–67 Offset
Pixels 34–67 Gain
Pixels 68–101 Offset
Pixels 68–101 Gain
Mode
8
5
8
5
8
5
4
2
3
4
5
1F
The offset registers are 8-bit signed offsets and the gain registers are 5-bit magnitudes. The programmed offset
correction is applied to the sampled energy, and then the gain is applied. (e.g., the gain will affect the offset
correction). These two registers allow the user to maximize the dynamic range achievable in the given system.
The mode register is used during factory testing and for future product enhancements. The user should always
program zeros into the mode register.
Copyright E 2000, TAOS Inc.
www.taosinc.com
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