TSL2301
102
×
1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG TO DIGITAL CONVERTER
TAOS007 – JULY 2000
Terminal Functions
TERMINAL
NAME
GND
SCLK
SDIN
SDOUT
V
DD
NO.
6, 7
1
3
4
2
I/O
Ground
Clock input for SDIN and SDOUT
Serial data input. Data is clocked in on the rising edge of CLK.
Serial data output. Data is clocked out on the falling edge of CLK.
Supply voltage, V
DD
is nominally 5 V.
DESCRIPTION
Detailed Description
The sensor consist of 102 photodiodes, also called pixels, arranged in a linear array. Light energy impinging
on the pixels generates a photocurrent, which is then integrated by the active integration circuitry associated
with each pixel. During the integration period, a sampling capacitor connects to the output of the integrator
through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light
intensity (E
e
) on that pixel and the integration time (t
int
).
The array is divided into three 34-pixel zones, with each zone having programmable gain and offset (dark signal)
correction. The offset correction is controlled by an 8-bit DAC and is performed in the analog domain prior to
the digital conversion. There is a separate offset DAC for each of the three zones. The offset value is signed,
with codes 0 – 7Fh corresponding to positive offset values and codes 80h – FFh corresponding to increasingly
negative offset values. Offset adjustments should be made before setting the gain, but may have to be
readjusted after the gain changes are made. The gain adjustment is controlled by a 5-bit DAC, with positive gain
values ranging from 0 to 1Fh. There is a separate gain DAC for each of the three zones. Table 1 lists the gain
settings and the resulting gain change.
Integration, sampling, output, and reset of the integrators are performed by the control logic in response to
commands input via the SDIN pin. A normal sequence of operation consists of a pixel reset (RESET), start of
integration (STARTInt), sampling of integrators (SAMPLEInt), and pixel output (READPixel). Reset sets all the
integrators to zero. Start of integration releases the integrators from the reset state and defines the beginning
of the integration period. Sampling the integrators ends the integration period and stores the charge
accumulated in each pixel in a sample and hold circuit. Reading the pixels causes the sampled value of each
pixel to be converted to 8-bit digital format and output on the SDOUT pin. All 102 pixels are output sequentially
unless interrupted by an abort (ABORTPixel) command or reset by a RESET command.
The commands coming from the controller via the SDIN line are synchronous with the SCLK, which nominally
operates at 10 MHz. The protocol for both the data and control words employs the USART convention of
start/stop delimiters. There is one start bit and one stop bit.
Copyright
E
2000, TAOS Inc.
t
www.taosinc.com
2
t
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
