TPA6130A2
www.ti.com
SLOS488B–NOVEMBER 2006–REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
|VOS|
PSRR
Output offset voltage
VDD = 2.5 V to 5.5 V, inputs grounded
VDD = 2.5 V to 5.5 V, inputs grounded
VDD = 2.5 V to 5.5 V
150 400
µV
dB
dB
Power supply rejection ratio
–109 –90
CMRR Common mode rejection ratio
–68
SCL, SDA
SD
1
|IIH
|
High-level input current
Low-level input current
VDD = 5.5 V, VI = VDD
µA
10
1
|IIL|
VDD = 5.5 V, VI = 0 V
SCL, SDA, SD
µA
mA
µA
µA
VDD = 2.5 V to 5.5 V, SD = VDD
4
0.4
25
6
1
Shutdown mode, VDD = 2.5V to 5.5 V, SD = 0 V
SW Shutdown mode, VDD = 2.5V to 5.5 V, SWS = 1
IDD
Supply current
75
Both HP amps disabled, VDD = 2.5V to 5.5 V,
SWS = 0, Charge Pump enabled, SD = VDD
1.4
2.5
mA
TIMING CHARACTERISTICS(1)(2)
For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
Frequency, SCL
TEST CONDITIONS
MIN
TYP
MAX
400
UNIT
kHz
µs
fSCL
tw(H)
tw(L)
tsu1
th1
No wait states
Pulse duration, SCL high
0.6
1.3
300
10
Pulse duration, SCL low
µs
Setup time, SDA to SCL
ns
Hold time, SCL to SDA
ns
t(buf)
tsu2
th2
Bus free time between stop and start condition
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
1.3
0.6
0.6
0.6
µs
µs
µs
tsu3
µs
(1) VPull-up = VDD
(2) A pull-up resistor ≤2 kΩ is required for a 5 V I2C bus voltage.
t
t
w(L)
w(H)
SCL
t
h1
t
su1
SDA
Figure 1. SCL and SDA Timing
Copyright © 2006–2008, Texas Instruments Incorporated
5
Product Folder Link(s): TPA6130A2
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