TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
Command Register
The command register specifies the address of the target register for subsequent read and write operations.
This register contains eight bits as described in Table 3 and defaults to 00h at power on.
Table 3. Command Register
7
CMD
0
6
5
4
3
2
ADDRESS
0
1
0
0
0
COMMAND
TRANSACTION
Reset Value:
0
0
0
0
FIELD
BITS
DESCRIPTION
CMD
7
Select command register. Must write as 1.
Transaction. Selects type of transaction to follow in subsequent data transfer.
FIELD VALUE
TRANSACTION
Byte protocol
Word protocol
Block protocol
DESCRIPTION
SMB read/write byte protocol
SMB read/write word protocol
SMB read/write block protocol
00
01
10
TRANSACTION
6:5
Clear any pending interrupt and is a write-
once-to-clear field
11
Interrupt clear
Register Address. This field selects the specific control or status register for following write and read com-
mands according to Table 2.
ADDRESS
4:0
2
2
NOTES: 1. An I C block transaction will continue until the Master sends a stop condition. See Figure 18 and Figure 19. Unlike the I C protocol,
the TCS3404/14 SMBus read/write protocol requires a Byte Count. All eight ADC Channel Data Registers (10h through 17h) can
be read simultaneously in a single SMBus transaction. This is the only 64-bit data block supported by the TCS3404 SMBus protocol.
The TRANSACTION field must be set to 10, and a read condition should be initiated with a COMMAND CODE of CFh. By using
a COMMAND CODE of CFh during an SMBus Block Read Protocol, the TCS3404 device will automatically insert the appropriate
Byte Count (Byte Count = 8) as illustrated in Figure 18. A write condition should not be used in conjunction with the 0Fh register.
2. Only the Send Byte Protocol should be used when clearing interrupts.
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
r
r
14
www.taosinc.com
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
