TAS2521
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SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013
3.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.5
1.65
2.7
1.1
4
NOM
1.8
MAX
1.95
1.95
5.5
UNIT
AVDD(1)
DVDD
SPKVDD(1)
Referenced to AVSS(2)
Power-supply voltage range
(2)
Referenced to DVSS
1.8
V
(2)
Referenced to SPKVSS
(2)
IOVDD
Referenced to IOVSS
1.8
3.6
Speaker impedance
Load applied across class-D output pins (BTL)
AC-coupled to RL
Ω
Ω
Headphone impedance
16
Analog audio full-scale input
voltage
VI
AVDD = 1.8 V, single-ended
0.5
10
VRMS
Line output load impedance
(in half drive ability mode)
AC-coupled to RL
kΩ
MCLK(3)
SCL
Master clock frequency
SCL clock frequency
IOVDD = DVDD = 1.8V
50
400
85
MHz
kHz
°C
TA
Operating free-air temperature
–40
(1) To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level.
(2) All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground
signals. By use of a wide trace or ground plane, ensure a low-impedance connection between AVSS and DVSS.
(3) The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.
3.4 Electrical Characteristics
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INTERNAL OSCILLATOR—RC_CLK
Oscillator frequency
8.48
MHz
Audio DAC – Stereo Single-Ended Headphone Output
Load = 16Ω (single-ended), Input & Output CM =
0.9V, DOSR = 128, Device Setup MCLK = 256* fs,
Channel Gain = 0dB word length = 16 bits;
Processing Block = PRB_P1 Power Tune =
PTM_P3
Device Setup
Full-scale output voltage (0 dB)
Idle channel noise
0.5
20.7
-78.2
103.7
47.2
88.1
±0.3
11
Vrms
μVms
dB
ICN
Measured as idle-channel noise, A-weighted(1) (2)
THD+N
Total harmonic distortion + noise 0-dBFS input, 1-kHz input signal
Mute attenuation
Power-supply rejection ratio(3)
Dynamic range, A-weighted(1) (2) –60dB 1kHz input full-scale signal
Mute
dB
PSRR
DR
Ripple on AVDD (1.8 V) = 200 mVPP at 1 kHz
dB
Gain error
0dB, 1kHz input full scale signal
RL = 32 Ω, THD+N ≤ –40 dB
RL = 16 Ω, THD+N ≤ –40 dB
dB
PO
Maximum output power
mW
18
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) DAC to headphone-out PSRR measurement is calculated as PSRR = 20 X log(∆VHP / ∆VAVDD).
Copyright © 2013, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
5
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