TAS2521
SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013
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The signal-processing blocks available are:
•
•
First-order IIR
Scalable number of biquad filters
The processing blocks are tuned for common cases and can achieve high image rejection or low group
delay in combination with various signal-processing effects such as audio effects and frequency shaping.
The available first-order IIR and biquad filters have fully user-programmable coefficients.
Table 5-2. Overview – DAC Predefined Processing Blocks
Processing
Block No.
First-Order
IIR Available
Number of
Biquads
Resource
Class
Interpolation Filter
Channel
PRB_P1
PRB_P2
PRB_P3
A
A
B
Mono
Mono
Mono
Yes
No
6
3
6
6
4
4
Yes
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.2 Digital Mixing and Routing
The TAS2521 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the
digital audio data. The first mixer/multiplexer can be used to select input data for the mono DAC from left
channel, right channel, or (left channel + right channel) / 2 mixing. This digital routing can be configured by
writing to page 0, register 63, bits D5–D4.
5.6.3 Analog Audio Routing
The TAS2521 has the capability to route the DAC output to either the headphone or the speaker output. If
desirable, both output drivers can be operated at the same time while playing at different volume levels.
The TAS2521 provides various digital routing capabilities, allowing digital mixing or even channel
swapping in the digital domain. All analog outputs other than the selected ones can be powered down for
optimal power consumption.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.4 5V LDO
The TAS2521 has a built-in LDO which can generate the analog supply (AVDD) also the digital supply
(DVDD) from input voltage range of 2.7 V to 5.5 V with high PSRR. If combined power supply current is
50 mA or less, then this LDO can deliver power to both analog and digital power supplies. If the only
speaker power supply is present and LDO Select pin is enabled, the LDO can power up without requiring
other supplies. This LDO requires a minimum dropout voltage of 300 mV and can support load currents up
to 50 mA. For stability reasons the LDO requires a minimum decoupling capacitor of 1 µF (±50%) on the
analog supply (AVDD) pin and the digital supply (DVDD) pin. If use this LDO output voltage for the digital
supply (DVDD) pin, the analog supply (AVDD) pin connected to the digital supply (DVDD) externally is
required.
The LDO is by default powered down for low sleep mode currents and can be enabled driving the
LDO_SELECT pin to SPKVDD (Speaker power supply). When the LDO is disabled the AVDD pin is tri-
stated and the device AVDD needs to be powered using external supply. In that case the DVDD pin is
also tri-stated and the device DVDD needs to be powered using external supply. The output voltage of this
LDO can be adjusted to a few different values as given in the Table 5-3.
22
Application Overview
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