TAS2521
SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013
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5.6.7.2.1 I2C Control Mode
The TAS2521 supports the I2C control protocol, and will respond to the I2C address of 0011 000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is
driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously,
there is no driver contention.
5.6.7.2.2 SPI Digital Interface
In the SPI control mode,the TAS2521 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO,
SDA/MOSI=MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI
control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host
processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor)
generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices
(such as the TAS2521) depend on a master to start and synchronize transmissions. A transmission begins
when initiated by an SPI master.The byte from the SPI master begins shifting in on the slave MOSI pin
under the control of the master serial clock(driven onto SCLK). As the byte shifts in on the MOSI pin, a
byte shifts out on the MISO pin to the master shif tregister.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.3 Power Supply
The TAS2521 integrates a large amount of digital and analog functionality, and each of these blocks can
be powered separately to enable the system to select appropriate power supplies for desired performance
and power consumption. The device has separate power domains for digital IO, digital core, analog core,
analog input, headphone driver, and speaker drivers. If desired, all of the supplies (except for the supplies
for speaker drivers, which can directly connect to the battery) can be connected together and be supplied
from one source in the range of 1.65 to 1.95V. Individually, the IOVDD voltage can be supplied in the
range of 1.1V to 3.6V. For improved power efficiency, the digital core power supply can range from 1.26V
to 1.95V. The analog core supply can either be derived from the internal LDO accepting an SPKVDD
voltage in the range of 2.7V to 5.5V, or the AVDD pin can directly be driven with a voltage in the range of
1.5V to 1.95V. The speaker driver voltages (SPKVDD) can range from 2.7V to 5.5V.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.4 Device Special Functions
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Interrupt generation
Flexible pin multiplexing
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.5 miniDSP
The TAS2521 features a miniDSP core which is tightly coupled to the DAC. The fully programmable
algorithms for the miniDSP must be loaded into the device after power up. The miniDSP has direct access
to the digital audio stream, offering the possibility for advanced, very low-group-delay DSP algorithms. The
miniDSP has 512 programmable instructions, 896 data memory locations, and 512 programmable
coefficients (in the adaptive mode, each bank has 256 programmable coefficients).
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Application Overview
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