TAS2521
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SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013
5.2 Circuit Configuration with Internal LDO
SVDD
IOVDD
0.1mF
0.1mF
22mF
10mF
0.1mF
22mF
2.7k
2.7k
DVSS
AVDD
DVDD
AVSS
LDO_SEL SPKVSS
SPKVDD
GPIO/DOUT
SDA/MOSI
SCL/SSZ
MCLK
8-W or
4-W
Speaker
SPKP
SPKM
WCLK
DIN
TAS2521
BCLK
RST
HPOUT
0.1mF
0.1mF
47mF
AINL
AINR
MISO
Analog Input
SCLK
SPI_SEL
IOVDD IOVSS
IOVDD
0.1mF
10mF
Figure 5-2. Application Schematics for LDO
5.3 Device Connections
5.3.1 Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins
have a default function, and also can be reprogrammed to cover alternative functions for various
applications.
The fixed-function pins are RST LDO_SEL and the SPI_SEL pin, which are HW control pins. Depending
on the state of SPI_SEL, the two control-bus pins SCL/SSZ and SDA/MOSI are configured for either I2C
or SPI protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Section 5.3.3.
5.3.2 Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog
blocks are powered down by default. The blocks can be powered up with fine granularity according to the
application needs.
Copyright © 2013, Texas Instruments Incorporated
Application Overview
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