TAS2521
SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013
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3.5.6 SPI Interface Timing
SS
S
t
td
tLag
t
tLead
sck
tf
tr
SCLK
MISO
tsckl
tsckh
tv(DOUT)
tdis
MSB OUT
thi
BIT 6 . . . 1
LSB OUT
t
a
tsu
MOSI
MSB IN
BIT 6 . . . 1
LSB IN
Figure 3-6. SPI Interface Timing Diagram
Timing Requirements
At 25°C, DVDD = 1.8V
Table 3-1. SPI Interface Timing
PARAMETER
TEST CONDITION
IOVDD=1.8V
MIN TYP MAX
IOVDD=3.3V
MIN TYP
UNITS
MAX
(1)
tsck
tsckh
tsckl
tlead
tlag
td
SCLK Period
100
50
50
30
30
40
50
25
25
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Pulse width High
SCLK Pulse width Low
Enable Lead Time
Enable Lag Time
Sequential Transfer Delay
Slave DOUT access time
Slave DOUT disable time
DIN data setup time
DIN data hold time
ta
40
40
40
40
tdis
tsu
15
15
15
10
thi
tv;DOUT DOUT data valid time
25
4
18
4
tr
tf
SCLK Rise Time
SCLK Fall Time
4
4
(1) These parameters are based on characterization and are not tested in production.
14
ELECTRICAL SPECIFICATIONS
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