TAS2521
SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013
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3.5.4 DSP Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
WCLK
tS(WS)
th(WS)
tS(WS)
th(WS)
tL(BCLK)
tf
BCLK
tH(BCLK)
tS(DI)
tr
DIN
th(DI)
T0146-10
IOVDD = 1.8V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
35
35
8
MAX
MIN
35
35
8
MAX
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
ts(DI)
th(DI)
tr
BCLK high period
BCLK low period
WCLK setup
WCLK hold
DIN setup
ns
ns
ns
ns
ns
ns
ns
ns
8
8
8
8
DIN hold
8
8
Rise time
4
4
4
4
tf
Fall time
Figure 3-4. DSP Timing in Slave Mode
12
ELECTRICAL SPECIFICATIONS
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