TAS2521
www.ti.com
SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013
3.5.5 I2C Interface Timing
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
SDA
tBUF
tLOW
tr
tHIGH
tf
tHD;STA
SCL
tHD;STA
tSU;DAT
tHD;DAT
tSU;STO
tSU;STA
STO
STA
STA
STO
T0295-02
PARAMETER
SCL clock frequency
Standard-Mode
MIN TYP
Fast-Mode
UNITS
MAX
MIN
TYP
MAX
400
fSCL
0
100
0
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD;STA
4
0.8
μs
tLOW
tHIGH
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4
1.3
0.6
μs
μs
Setup time for a repeated START
condition
Data hold time: For I2C bus devices
tSU;STA
4.7
0
0.8
μs
tHD;DAT
tSU;DAT
tr
3.45
0
0.9
μs
ns
ns
ns
μs
Data setup time
250
100
SDA and SCL rise time
1000
300
20 + 0.1 Cb
20 + 0.1 Cb
0.8
300
300
tf
SDA and SCL fall time
tSU;STO
Set-up time for STOP condition
4
Bus free time between a STOP and
START condition
tBUF
Cb
4.7
1.3
μs
Capacitive load for each bus line
400
400
pF
Figure 3-5. I2C Interface Timing
Copyright © 2013, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
13
Submit Documentation Feedback
Product Folder Links: TAS2521
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
