C2510Fx / CC2511Fx
13.13 Watchdog Timer
The watchdog timer (WDT) is intended as a
recovery method in situations where the
software hangs. The WDT shall reset the
system when software fails to clear the WDT
within a selected time interval. The watchdog
can be used in applications where high
reliability is required. If the watchdog
function is not needed in an application, it is
possible to configure the watchdog timer to
be used as an interval timer that can be
used to generate interrupts at selected time
intervals.
selected timer interval value, the counter is
reset to 0x0000 and continues incrementing
its value. The watchdog clear sequence
consists
of
writing
1010
to
WDCTL.CLR[3:0] followed by writing 0101
to the same register bits within one half of a
watchdog clock period. If this complete
sequence is not performed, the watchdog
timer generates a reset signal for the
system. Note that as long as a correct
watchdog clear sequence begins within the
selected timer interval, the counter is reset
when the complete sequence has been
received.
The features of the watchdog timer are as
follows:
When the watchdog timer has been enabled
in watchdog mode, it is not possible to
change the mode by writing to the
WDCTL.MODE bit. The timer interval value
can be changed by writing to the
WDCTL.INT[1:0]bits.
• Four selectable timer intervals
• Watchdog mode
• Timer mode
• Interrupt request generation in timer
mode
Note that a change in the timer interval
value should be followed by a clearing of
the watchdog timer to avoid an unwanted
watchdog reset.
• Clock independent from system clock
The operation of the WDT module is
controlled by the WDCTL register. The
watchdog timer consists of a 15-bit counter
clocked by the one of the low speed
oscillators. Note that the content of the 15-bit
counter is not user-accessible. The content
of the 15-bit counter is reset to 0x0000 when
a PM2 or PM3 is entered.
In watchdog mode, the WDT does not
produce an interrupt request.
13.13.2 Timer Mode
To set the WDT in normal timer mode, the
WDCTL.MODE bit is set to 1. When register
bit WDCTL.EN is set to 1, the timer is started
and the counter starts incrementing. When
the counter reaches the selected interval
value, the IRCON2.WDTIF flag is asserted
and an interrupt request is generated if
watchdog timer interrupt is enabled
(IEN2.WDTIE=1).
13.13.1 Watchdog Mode
The watchdog timer is disabled after a
system reset. To set the WDT in watchdog
mode the WDCTL.MODEbit must be set to 0.
The watchdog timer counter starts
incrementing when the enable bit WDCTL.EN
is set to 1. When the timer is enabled in
watchdog mode it is not possible to disable
In timer mode, it is possible to clear the timer
contents by writing a 1 to WDCTL.CLR[0].
When the timer is cleared the contents of the
counter is set to 0x0000. The timer is
stopped by setting WDCTL.EN=0 and
the timer. Therefore, writing
a
0
to
WDCTL.EN has no effect if a 1 was already
written to this bit when WDCTL.MODE was 0.
The WDT operates with a watchdog timer
clock frequency of 32.768 kHz (low speed
crystal oscillator) or 32 - 36 kHz (calibrated
low power RC oscillator). The timer interval
depend on the count value settings (64, 512,
8192, and 32768 respectively) configured in
WDCTL.INT.
restarted
WDCTL.EN=1.
from
0x000
by
setting
The timer interval is set by the
WDCTL.INT[1:0] bits. In timer mode, a
reset will not be produced when the timer
interval value is reached.
If the counter reaches the selected timer
interval value (watchdog timeout), the
watchdog timer generates a reset signal for
the system. If a watchdog clear sequence is
performed before the counter reaches the
13.13.3 Watchdog Mode and Power Modes
In active mode and PM0 the WDT runs and
resets the chip upon timeout. To avoid reset,
SWRS055D
Page 150 of 243
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