C2510Fx / CC2511Fx
13.14 USART
USART0 and
communications interfaces that can be
operated separately in either asynchronous
UART mode or in synchronous SPI mode. The
two USARTs are identical in functionality but
are assigned to separate I/O pins. Refer to
Section 13.4 on Page 88 for I/O configuration.
USART1
are
serial
When
UxCSR.TX_BYTE bit is set to 1. The USARTx
TX complete CPU interrupt flag
the
transmission
ends,
the
(IRCON2.UTXxIF) is asserted when the
UxDBUF register is ready to accept new
transmit data, and an interrupt request is
generated if IEN2.UTXxIE=1. This happens
immediately after the transmission has been
started, hence a new data byte value can be
loaded into the data buffer while the byte is
being transmitted.
13.14.1
UART Mode
For asynchronous serial interfaces, the UART
mode is provided. In UART mode the interface
uses
a
two-wire or four-wire interface
13.14.1.2 UART Receive
consisting of the pins RXD and TXD, and
optionally RTS and CTS. The UART mode
includes the following features:
Data reception on the UART is initiated when a
1 is written to the UxCSR.RE bit. The UART
will then search for a valid start bit on the
RXDx input pin and set the UxCSR.ACTIVEbit
high. When a valid start bit has been detected
the received byte is shifted into the receive
register. The UxCSR.RX_BYTE bit and the
CPU interrupt flag, TCON.URXxIF, is set to 1
when the operation has completed and an
• 8 or 9 data bits
• Odd, even, or no parity
• Configurable start and stop bit level
• Configurable LSB or MSB first transfer
• Independent receive and transmit
interrupt
IEN0.URXxIE=1.
UxCSR.ACTIVE will go low.
request
is
generated
if
time
interrupts
At
the
same
• Independent receive and transmit DMA
triggers
The received data byte is available through the
UxDBUF register. When UxDBUF is read,
UxCSR.RX_BYTE is cleared by hardware.
• Parity and framing error status
The UART mode provides full duplex
asynchronous
transfers
and
the
synchronization of bits in the receiver does not
interfere with the transmit function. A UART
byte transfer consists of a start bit, eight data
bits, an optional ninth data or parity bit, and
one or two stop bits. Note that the data
transferred is referred to as a byte, although
the data can actually consist of eight or nine
bits.
13.14.1.3 UART Hardware Flow Control
Hardware flow control is enabled when the
UxUCR.FLOW bit is set to 1. The RTS output
will then be driven low when the receive
register is empty and reception is enabled.
Transmission of a byte will not occur before
the CTS input go low.
The UART operation is controlled by the
USART x Control and Status registers, UxCSR,
and the USART x UART Control register,
UxUCR, where x is the USART number, 0 or 1.
13.14.1.4 UART Character Format
If the BIT9and PARITYbits in register UxUCR
are set high, parity generation and detection is
enabled. The parity is computed and
transmitted as the ninth bit, and during
reception, the parity is computed and
compared to the received ninth bit. If there is a
parity error, the UxCSR.ERR bit is set high.
This bit is cleared when UxCSRis read.
The UART mode is selected when
UxCSR.MODEis set to 1.
13.14.1.1 UART Transmit
A UART transmission is initiated when the
USART
Receive/Transmit
Data
Buffer,
The number of stop bits to be transmitted is set
to one or two bits determined by the register bit
UxUCR.SPB. The receiver will always check for
one stop bit. If the first stop bit received during
reception is not at the expected stop bit level, a
framing error is signaled by setting register bit
UxCSR.FE high. UxCSR.FE is cleared when
UxDBUF register is written. The byte is
transmitted on the TXDx output pin. The
UxDBUFregister is double-buffered.
The UxCSR.ACTIVE bit goes high when the
byte transmission starts and low when it ends.
SWRS055D
Page 152 of 243
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