C2510Fx / CC2511Fx
RNDL (0xBC) – Random Number Generator Data Low Byte
Bit
Name
Reset
R/W
Description
[7:0]
RNDL[7:0]
0xFF
R/W
Random value/seed or CRC result, low byte
When used for random number generation writing this register twice will
seed the random number generator. Writing to this register copies the 8
LSBs of the LFSR to the 8 MSBs and replaces the 8 LSBs with the data
value written.
The value returned when reading from this register is the 8 LSBs of the
LSFR.
When used for random number generation, reading this register returns the 8
LSBs of the random number. When used for CRC calculations, reading this
register returns the 8 LSBs of the CRC result.
RNDH (0xBD) – Random Number Generator Data High Byte
Bit
Name
Reset
R/W
Description
[7:0]
RNDH[7:0]
0xFF
R/W
Random value or CRC result/input data, high byte
When written, a CRC16 calculation will be triggered, and the data value
written is processed starting with the MSB bit.
The value returned when reading from this register is the 8 MSBs of the
LSFR.
When used for random number generation, reading this register returns the 8
MSBs of the random number. When used for CRC calculations, reading this
register returns the 8 MSBs of the CRC result.
13.12 AES Coprocessor
can be processed. Before each block load, a
dedicated start command must be sent to the
coprocessor.
The CC2510Fx/CC2511Fx data encryption is
performed using a dedicated coprocessor
which supports the Advanced Encryption
Standard, AES. The coprocessor allows
encryption/decryption to be performed with
minimal CPU usage.
13.12.2 Key and IV
Before a key or IV/nonce load starts, an
appropriate load key or IV/nonce command
must be issued to the coprocessor. When
loading the IV it is important to also set the
correct mode.
The coprocessor has the following features:
• ECB, CBC, CFB, OFB, CTR, and CBC-
MAC modes.
• Hardware support for CCM mode
• 128-bits key and IV/Nonce
A key load or IV load operation aborts any
processing that could be running.
• DMA transfer trigger capability
The key, once loaded, stays valid until a key
reload takes place.
13.12.1 AES Operation
The IV must be downloaded before the
beginning of each message (not block).
To encrypt a message, the following procedure
must be followed:
Both key and IV are cleared by a reset of the
device and when PM2 or PM3 are entered.
• Load key
• Load initialization vector (IV)/nonce
13.12.3 Padding of Input Data
• Download and upload data for
AES works on blocks of 128 bits. If the last
block contains less than 128 bits, it must be
padded with zeros when written to the
coprocessor.
encryption/decryption.
The AES coprocessor works on blocks of 128
bits. A block of data is loaded into the
coprocessor, encryption is performed, and the
result must be read out before the next block
SWRS055D
Page 147 of 243
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