C2510Fx / CC2511Fx
• SSN: SS14
• MOSI: MO
• MISO: MI
responsibility to not assign more than two
peripherals to the same pin locations
P2SEL.PRI3P1,
P2SEL.PRI2P1,
P2SEL.PRI1P1, and P2SEL.PRI0P1 select
the order of precedence when assigning two,
and in some cases three, peripherals to P1.
UART:
• RXDATA: RX
• TXDATA: TX
• RTS: RT
When
P2SEL.PRI1P1
=
0
and
P2SEL.PRI0P1 = 1, Timer 1 has precedence
over Timer 4 and USART0 respectively. It is
the user’s responsibility to avoid configurations
where the order of precedence is not
conclusive.
• CTS: CT
P2DIR.PRIP0
selects
the
order
of
precedence when assigning two peripherals to
the same pin location on P0. When set to 01,
USART1 has precedence if both USART0 and
USART1 are assigned to the same pins. Note
that if USART1 is configured to operate in
UART mode with hardware flow control
disabled, USART0 or timer 1 will have
precedence to use ports P0_3 and P0_2. It is
the user’s responsibility to not assign more
than two peripherals to the same pin locations,
as P2DIR.PRIP0 will not give a conclusive
order of precedence if more than two
peripherals are in conflict on a pin.
13.4.6.4 Timer 3
PERCFG.T3CFG selects whether to use
alternative 1 or alternative 2 locations.
In Table 50, the Timer 3 signals are shown as
follows:
• Channel 0 compare pin: 0
• Channel 1 compare pin: 1
P2SEL.PRI3P1,
P2SEL.PRI2P1,
P2SEL.PRI1P1, and P2SEL.PRI0P1 select
the order of precedence when assigning two,
and in some cases three, peripherals to P1.
Setting P2SEL.PRI2P1 = 1 gives Timer 3
precedence over USART1. It is the user’s
responsibility to avoid configurations where the
order of precedence is not conclusive.
P2SEL.PRI3P1,
P2SEL.PRI2P1,
P2SEL.PRI1P1, and P2SEL.PRI0P1 select
the order of precedence when assigning two,
and in some cases three, peripherals to P1. By
setting PRI3P1 to 1 and PRI2P1 to 0,
USART1 will have precedence over both
USART0 and Timer 3. However, if USART1 is
configured to operate in UART mode with
hardware flow control disabled, there will be a
conflict on P1_4 between USART0 and Timer
3 (channel 1), which the P2SEL register
settings do not solve. It is the user’s
responsibility to avoid configurations where the
order of precedence is not conclusive.
13.4.6.5 Timer 4
PERCFG.T4CFG selects whether to use
alternative 1 or alternative 2 locations.
In Table 50, the Timer 4 signals are shown as
follows:
• Channel 0 compare pin: 0
• Channel 1 compare pin: 1
13.4.6.3 Timer 1
P2SEL.PRI3P1,
P2SEL.PRI2P1,
P2SEL.PRI1P1, and P2SEL.PRI0P1 select
the order of precedence when assigning two,
and in some cases three, peripherals to P1.
Setting P2SEL.PRI12P1 = 1 gives Timer 4
precedence over Timer 1. It is the user’s
responsibility to avoid configurations where the
order of precedence is not conclusive.
PERCFG.T1CFG selects whether to use
alternative 1 or alternative 2 locations.
In Table 50, the Timer 1 signals are shown as
follows:
• Channel 0 capture/compare pin: 0
• Channel 1 capture/compare pin: 1
• Channel 2 capture/compare pin: 2
13.4.6.6 I2S
The
I2S
configuration
register
bit
P2DIR.PRIP0
selects
the
order
of
I2SCFG1.IOLOC selects whether to use
alternative 1 or alternative 2 locations.
In Table 50, the I2S signals are shown as
follows:
precedence when assigning two peripherals to
the same pin location on P0. When set to 10
or 11, Timer 1 has precedence over USART1
and USART0 respectively. It is the user’s
SWRS055D
Page 91 of 243
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