C2510Fx / CC2511Fx
7.10 7-12 bit ADC
TA = 25 °C, VDD = 3.0V if nothing else stated. The numbers given here are based on tests performed
in accordance with IEEE Std 1241-2000 [7]. The ADC data are from CC2430 characterization. As the
CC2510x/C2511Fx uses the same ADC, the numbers listed in Table 18 should be good indicators of the
performance to be expected from CC2510x and CC2511x. Note that these numbers will apply for 24 MHz
operated systems (like CC2510x using a 24 MHz crystal or CC2511x using a 48 MHz crystal).
Performance will be slightly different for other crystal frequencies (e.g. 26 MHz and 27 MHz).
Parameter
Min
Typ
Max
Unit Condition/Note
Input voltage
0
0
0
AVDD
AVDD
AVDD
V
V
V
AVDD is voltage on AVDD pin
External reference voltage
AVDD is voltage on AVDD pin
AVDD is voltage on AVDD pin
External reference voltage
differential
Input resistance, signal
197
Simulated using 4 MHz clock speed (see Section
13.10.2.7)
kΩ
Full-Scale Signal4
ENOB4
2.97
5.7
V
Peak-to-peak, defines 0 dBFS
7-bits setting
bits
Single ended input
7.5
9-bits setting
9.3
10-bits setting
10.8
6.5
12-bits setting
ENOB4
bits
7-bits setting
Differential input
8.3
9-bits setting
10.0
11.5
0-20
10-bits setting
12-bits setting
Useful Power Bandwidth
THD4
kHz
7-bits setting, both single and differential
-Single ended input
-Differential input
-75.2
-86.6
dB
dB
12-bits setting, -6 dBFS
12-bits setting, -6 dBFS
Signal To Non-Harmonic Ratio4
-Single ended input
-Differential input
70.2
79.3
dB
dB
12-bits setting
12-bits setting
Spurious Free Dynamic Range4
-Single ended input
-Differential input
78.8
88.9
<-84
dB
dB
dB
12-bits setting, -6 dBFS
12-bits setting, -6 dBFS
CMRR, differential input
12- bit setting, 1 kHz Sine (0 dBFS), limited by ADC
resolution
Crosstalk, single ended input
<-84
dB
12- bit setting, 1 kHz Sine (0 dBFS), limited by ADC
resolution
Offset
-3
mV
%
Mid. Scale
Gain error
DNL4
0.68
0.05
0.9
LSB 12-bits setting, mean
LSB 12-bits setting, max
LSB 12-bits setting, mean
LSB 12-bits setting, max
INL4
4.6
13.3
35.4
SINAD4
dB
7-bits setting
4 Measured with 300 Hz Sine input and VDD as reference.
SWRS055D
Page 20 of 243
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