CC2430
8051 CPU : Memory
XDATA
Register name
Description
Address
0xDF54
FSMTC1
-
Finite State Machine Control
Reserved
0xDF55-
0xDF5F
0xDF60
0xDF61
0xDF62
0xDF63
0xDF64
CHVER
Chip Version
Chip Identification
RF Status
CHIPID
RFSTATUS
-
Reserved
IRQSRC
-
RF Interrupt Source
Reserved
0xDF65-
0xDFFF
11.2.4
XDATA Memory Access
In some 8051 implementations, this type of
XDATA access is performed using P2 to give
the most significant address bits. Existing
software may therefore have to be adapted to
make use of MPAGE instead of P2.
The CC2430 provides an additional SFR
register MPAGE. This register is used during
instructions MOVX A,@Ri and MOVX @Ri,A.
MPAGE gives the 8 most significant address
bits, while the register Ri gives the 8 least
significant bits.
MPAGE (0x93) – Memory Page Select
Bit
Name
Reset
R/W
Description
7:0
0x00
R/W
MPAGE[7:0]
Memory page, high-order bits of address in MOVX
instruction
11.2.5
Memory Arbiter
For the 128 KB flash version (CC2430-F128),
the Flash Bank Map register, FMAP, controls
mapping of physical banks of the 128 KB flash
to the program address region 0x8000-0xFFFF
in CODE memory space as shown in Figure 8
on 32.
The CC2430 includes a memory arbiter which
handles CPU and DMA access to all physical
memory.
The control registers MEMCTR and FMAP are
used to control various aspects of the memory
sub-system. The MEMCTR and FMAP registers
are described below.
Please note that the FMAP.MAP[1:0] and
MEMCTR.FMAP[1:0] bits are aliased. Writing
to FMAP.MAP[1:0] will also change the
contents of the MEMCTR.FMAP[1:0] bits, and
vice versa.
MEMCTR.MUNIF controls unified mapping of
CODE memory space as shown in Figure 8
and Figure 9 on page 32. Unified mapping is
required when the CPU is to execute program
stored in RAM (XDATA).
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 40 of 211
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