CC2430
8051 CPU : Memory
Table 26: RFR address overview (XDATA addressable with offset DF00h)
DF+
00
8 bytes
DF+
07
0F
17
1F
27
2F
37
3F
47
4F
57
5F
67
6F
77
7F
-
-
MDMCTRL0H
MDMCTRL0L
MDMCTRL1H
MDMCTRL1L
RSSIH
RSSIL
08
10
18
20
28
30
38
40
48
50
58
60
68
70
78
SYNCHWORDH
SYNCWORDL
TXCTRLH
TXCTRLL
RXCTRL0H
RXCTRL0L
RXCTRL1H
RXCTRL1L
FSCTRLH
FSCTRLL
CSPX
CSPY
CSPZ
CSPCTRL
CSPT
RFPWR
-
-
-
-
-
-
-
-
FSMTCH
FSMTCL
MANANDH
MANANDL
MANORH
MANORL
AGCCTRLH
AGCCTRLL
AGCTST0H
AGCTS0L
AGCTST1H
AGCTST1L
AGCTST2H
AGCTST2L
FSTST0H
FSTST0L
FSTST1H
FSTST1L
FSTST2H
FSTST2L
FSTST3H
FSTST3L
-
RXBPFTSTH
RXBPFTSTL
FSMSTATE
ADCTSTH
ADCTSTL
DACTSTH
DACTSTL
-
TOPTST
RESERVEDH
RESERVEDL
-
IEEE_ADDR0
IEEE_ADDR1
IEEE_ADDR2
IEEE_ADDR3
IEEE_ADDR4
IEEE_ADDR5
IEEE_ADDR6
IEEE_ADDR7
PANIDH
PANIDL
SHORTADDRH
SHORTADDRL
IOCFG0
IOCFG1
IOCFG2
IOCFG3
RXFIFOCNT
FSMTC1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CHVER
CHIPID
RFSTATUS
IRQSRC
-
-
-
-
-
-
-
-
-
-
-
-
Table 27 : Overview of RF registers
XDATA
Register name
Description
Address
0xDF00-
0xDF01
-
Reserved
0xDF02
0xDF03
0xDF04
0xDF05
0xDF06
0xDF07
0xDF08
0xDF09
0xDF0A
0xDF0B
0xDF0C
0xDF0D
0xDF0E
0xDF0F
0xDF10
0xDF11
0xDF12
0xDF13
0xDF14
0xDF15
MDMCTRL0H
MDMCTRL0L
MDMCTRL1H
MDMCTRL1L
RSSIH
Modem Control 0, high
Modem Control 0, low
Modem Control 1, high
Modem Control 1, low
RSSI and CCA Status and Control, high
RSSI and CCA Status and Control, low
Synchronisation Word Control, high
Synchronisation Word Control, low
Transmit Control, high
RSSIL
SYNCWORDH
SYNCWORDL
TXCTRLH
TXCTRLL
RXCTRL0H
RXCTRL0L
RXCTRL1H
RXCTRL1L
FSCTRLH
FSCTRLL
CSPX
Transmit Control, low
Receive Control 0, high
Receive Control 0, low
Receive Control 1, high
Receive Control 1, low
Frequency Synthesizer Control and Status, high
Frequency Synthesizer Control and Status, low
CSP X Data
CSPY
CSP Y Data
CSPZ
CSP Z Data
CSPCTRL
CSP Control
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 38 of 211
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