CC2430
8051 CPU : Memory
Table 24: SFR address overview
8 bytes
80
88
90
98
P0
SP
DPL0
P1IFG
DPS
DPH0
DPL1
DPH1
U0CSR
PCON
P0INP
ST2
87
8F
97
9F
A7
AF
B7
BF
TCON
P1
P0IFG
RFIM
-
P2IFG
MPAGE
S1CON
T2OF2
FWT
PICTL
P1IEN
-
T2CMP
ST0
ST1
S0CON
IEN2
T2PEROF0
T2CAPLPL
FADDRL
ADCCON1
RNDL
T2PEROF1
T2CAPHPH
FADDRH
ADCCON2
RNDH
T2PEROF2 FMAP
A0 P2
T2OF0
IP0
T2OF1
-
T2TLD
T2THD
A8 IEN0
FCTL
FWDATA
B0
-
ENCDI
IP1
ENCDO
ADCL
U0BAUD
T3CNT
ENCCS
ADCH
T2CNF
T3CTL
ADCCON3
SLEEP
-
-
B8 IEN1
C0 IRCON
U0DBUF
WDCTL
DMAIRQ
RFD
U0UCR
U0GCR
T3CC0
CLKCON
T3CCTL1
MEMCTR C7
T3CC1 CF
DMAREQ D7
T1CC2H DF
T1CCTL2 E7
C8
-
T3CCTL0
D0 PSW
D8 TIMIF
E0 ACC
DMA1CFGL DMA1CFGH DMA0CFGL DMA0CFGH DMAARM
T1CC0L
T1CNTL
T4CNT
T1CC0H
T1CNTH
T4CTL
T1CC1L
T1CTL
T1CC1H
T1CCTL0
T4CC0
T1CC2L
T1CCTL1
T4CCTL1
P1INP
RFST
RFIF
E8 IRCON2
T4CCTL0
P1SEL
T4CC1
P2INP
P2DIR
EF
F7
FF
F0
B
PERCFG ADCCFG
P0SEL
P2SEL
F8 U1CSR
U1DBUF
U1BAUD
U1UCR
U1GCR
P0DIR
P1DIR
Table 25: CC2430 specific SFR overview
Register name
SFR
Module
Description
Address
ADCCON1
ADCCON2
ADCCON3
ADCL
0xB4
0xB5
0xB6
0xBA
0xBB
0xBC
0xBD
0xB1
0xB2
0xB3
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xAB
0xAC
0xAD
0xAE
0xAF
0x89
ADC
ADC Control 1
ADC
ADC Control 2
ADC
ADC Control 3
ADC
ADC Data Low
ADCH
ADC
ADC Data High
RNDL
ADC
Random Number Generator Data Low
Random Number Generator Data High
Encryption/Decryption Input Data
Encryption/Decryption Output Data
Encryption/Decryption Control and Status
DMA Interrupt Flag
RNDH
ADC
ENCDI
AES
ENCDO
ENCCS
AES
AES
DMAIRQ
DMA1CFGL
DMA1CFGH
DMA0CFGL
DMA0CFGH
DMAARM
DMAREQ
FWT
DMA
DMA
DMA
DMA
DMA
DMA
DMA
FLASH
FLASH
FLASH
FLASH
FLASH
IOC
DMA Channel 1-4 Configuration Address Low
DMA Channel 1-4 Configuration Address High
DMA Channel 0 Configuration Address Low
DMA Channel 0 Configuration Address High
DMA Channel Armed
DMA Channel Start Request and Status
Flash Write Timing
FADDRL
FADDRH
FCTL
Flash Address Low
Flash Address High
Flash Control
FWDATA
P0IFG
Flash Write Data
Port 0 Interrupt Status Flag
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 35 of 211
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