CC2430
17 Register overview
ACC (0xE0) – Accumulator...................................................................................................................43
ADCCFG (0xF2) – ADC Input Configuration ........................................................................................83
ADCCON1 (0xB4) – ADC Control 1....................................................................................................131
ADCCON2 (0xB5) – ADC Control 2....................................................................................................132
ADCCON3 (0xB6) – ADC Control 3....................................................................................................133
ADCH (0xBB) – ADC Data High .........................................................................................................131
ADCL (0xBA) – ADC Data Low...........................................................................................................130
ADCTSTH (0xDF3A)...........................................................................................................................196
ADCTSTL (0xDF3B) ...........................................................................................................................196
AGCCTRLH (0xDF26) ........................................................................................................................196
AGCCTRLL (0xDF27).........................................................................................................................196
B (0xF0) – B Register............................................................................................................................43
CHIPID (0xDF61)................................................................................................................................200
CHVER (0xDF60)................................................................................................................................200
CLKCON (0xC6) – Clock Control..........................................................................................................70
CSPCTRL (0xDF15) ...........................................................................................................................193
CSPT (0xDF16)...................................................................................................................................192
CSPX (0xDF12) ..................................................................................................................................192
CSPY (0xDF13) ..................................................................................................................................193
CSPZ (0xDF14)...................................................................................................................................193
DACTSTH (0xDF3C)...........................................................................................................................197
DACTSTL (0xDF3D) ...........................................................................................................................197
DMA0CFGH (0xD5) – DMA Channel 0 Configuration Address High Byte...........................................97
DMA0CFGL (0xD4) – DMA Channel 0 Configuration Address Low Byte ............................................97
DMAARM (0xD6) – DMA Channel Arm ................................................................................................96
DMAIRQ (0xD1) – DMA Interrupt Flag .................................................................................................98
DMAREQ (0xD7) – DMA Channel Start Request and Status...............................................................97
DPH0 (0x83) – Data Pointer 0 High Byte..............................................................................................42
DPH1 (0x85) – Data Pointer 1 High Byte..............................................................................................42
DPL0 (0x82) – Data Pointer 0 Low Byte...............................................................................................42
DPL1 (0x84) – Data Pointer 1 Low Byte...............................................................................................42
DPS (0x92) – Data Pointer Select ........................................................................................................42
ENCCS (0xB3) – Encryption Control and Status................................................................................140
ENCDI (0xB1) – Encryption Input Data...............................................................................................140
ENCDO (0xB2) – Encryption Output Data..........................................................................................140
FADDRH (0xAD) – Flash Address High Byte .......................................................................................77
FADDRL (0xAC) – Flash Address Low Byte.........................................................................................77
FCTL (0xAE) – Flash Control................................................................................................................77
FSCTRLH (0xDF10)............................................................................................................................192
FSCTRLL (0xDF11) ............................................................................................................................192
FSMSTATE (0xDF39).........................................................................................................................196
FSMTC1 (0xDF54)..............................................................................................................................200
FSMTCH (0xDF20) .............................................................................................................................194
FSMTCL (0xDF21)..............................................................................................................................194
FWDATA (0xAF) – Flash Write Data ....................................................................................................77
FWT (0xAB) – Flash Write Timing ........................................................................................................77
IEEE_ADDR0 (0xDF43)......................................................................................................................197
IEEE_ADDR1 (0xDF44)......................................................................................................................197
IEEE_ADDR2 (0xDF45)......................................................................................................................197
IEEE_ADDR3 (0xDF46)......................................................................................................................197
IEEE_ADDR4 (0xDF47)......................................................................................................................197
IEEE_ADDR5 (0xDF48)......................................................................................................................198
IEEE_ADDR6 (0xDF49)......................................................................................................................198
IEEE_ADDR7 (0xDF4A) .....................................................................................................................198
IEN0 (0xA8) – Interrupt Enable 0..........................................................................................................52
IEN2 (0x9A) – Interrupt Enable 2..........................................................................................................53
IOCFG0 (0xDF4F)...............................................................................................................................198
IOCFG1 (0xDF50)...............................................................................................................................199
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 203 of 211
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