CC2430
Radio : Radio Registers
DACTSTH (0xDF3C)
Bit
Name
Reset
R/W
Description
Reserved, read as 0.
7
-
0
R0
The TX DACs data source is selected by DAC_SRC
according to:
6:4
DAC_SRC[2:0]
000
R/W
000 : Normal operation (from modulator).
001 : The DAC_I_O and DAC_Q_O override values below.-
010 : From ADC, most significant bits
011 : I/Q after digital down mix and channel filtering.
100 : Full-spectrum White Noise (from CRC)
101 : From ADC, least significant bits
110 : RSSI / Cordic Magnitude Output
111 : HSSD module.
This feature will often require the DACs to be manually
turned on in MANOVR and
PAMTST.ATESTMOD_MODE=4.
I-branch DAC override value.
3:0
DAC_I_O[5:2]
000
R/W
DACTSTL (0xDF3D)
Bit
Name
Reset
R/W
Description
I-branch DAC override value.
Q-branch DAC override value.
7:6
5:0
DAC_I_O[1:0]
DAC_Q_O[5:0]
00
R/W
R/W
0x00
IEEE_ADDR0 (0xDF43)
Bit
Name
Reset
R/W
Description
IEEE ADDR byte 0 (LSB)
7:0
IEEE_ADDR0[7:0]
0x00
R/W
IEEE_ADDR1 (0xDF44)
Bit
Name
Reset
R/W
Description
IEEE ADDR byte 1
7:0
IEEE_ADDR1[7:0]
0x00
R/W
IEEE_ADDR2 (0xDF45)
Bit
Name
Reset
R/W
Description
IEEE ADDR byte 2
7:0
IEEE_ADDR2[7:0]
0x00
R/W
IEEE_ADDR3 (0xDF46)
Bit
Name
Reset
R/W
Description
IEEE ADDR byte 3
7:0
IEEE_ADDR3[7:0]
0x00
R/W
IEEE_ADDR4 (0xDF47)
Bit
Name
Reset
R/W
Description
IEEE ADDR byte 4
7:0
IEEE_ADDR4[7:0]
0x00
R/W
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 197 of 211