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CC2430F32RTC 参数 Datasheet PDF下载

CC2430F32RTC图片预览
型号: CC2430F32RTC
PDF下载: 下载PDF文件 查看货源
内容描述: 真正的系统级芯片解决方案的2.4 GHz IEEE 802.15.4 / ZigBee的 [A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee]
分类和应用: 电信集成电路
文件页数/大小: 212 页 / 1862 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC2430  
Radio : Receive mode  
event that causes a RADIO DMA trigger, is  
when data is read from the RXFIFO (through  
RFD SFR register) and there is still more data  
available in the RXFIFO.  
14.7 Receive mode  
In receive mode, the interrupt flag  
RFIF.IRQ_SFD goes high and the RF  
interrupt is requested after the start of frame  
delimiter (SFD) field has been completely  
received. If address recognition is disabled or  
is successful, the RFSTATUS.SFDbit goes low  
again only after the last byte of the MPDU has  
been received. If the received frame fails  
address recognition, the RFSTATUS.SFD bit  
goes low immediately. This is illustrated in  
Figure 35.  
number of bytes in the RXFIFO exceeds the  
programmed threshold.  
The RFSTATUS.FIFOP bit will also go high  
when the last byte of a new packet is received,  
even if the threshold is not exceeded. If so the  
RFSTATUS.FIFOPbit will go back to low once  
one byte has been read out of the RXFIFO.  
When address recognition is enabled, data  
should not be read out of the RXFIFO before  
the address is completely received, since the  
frame may be automatically flushed by CC2430  
if it fails address recognition. This may be  
handled by using the RFSTATUS.FIFOP bit,  
since this bit does not go high until the frame  
passes address recognition.  
The RFSTATUS.FIFObit is high when there is  
one or more data bytes in the RXFIFO. The  
first byte to be stored in the RXFIFO is the  
length field of the received frame, i.e. the  
RFSTATUS.FIFO bit is set high when the  
length field is written to the RXFIFO. The  
RFSTATUS.FIFO bit then remains high until  
the RXFIFO is empty. The RF register  
RXFIFOCNT contains the number of bytes  
present in the RXFIFO.  
Figure 36 shows an example of status bit  
activity when reading a packet from the  
RXFIFO. In this example, the packet size is 8  
bytes, IOCFG0.FIFOP_THR  
=
3
and  
MDMCTRL0L.AUTOCRC is set. The length will  
be 8 bytes, RSSI will contain the average  
RSSI level during receiving of the packet and  
FCS/corr contains information of FCS check  
result and the correlation levels.  
The RFSTATUS.FIFOP bit is high when the  
number of unread bytes in the RXFIFO  
exceeds the threshold programmed into  
IOCFG0.FIFOP_THR.  
When  
address  
recognition is enabled the RFSTATUS.FIFOP  
bit will not go high until the incoming frame  
passes address recognition, even if the  
14.8 RXFIFO overflow  
The RXFIFO can only contain a maximum of  
128 bytes at a given time. This may be divided  
between multiple frames, as long as the total  
number of bytes is 128 or less. If an overflow  
occurs in the RXFIFO, this is signaled to the  
CPU by asserting the RFERR interrupt when  
enabled. In addition the radio will set  
the RXFIFO will not be affected by the  
overflow, i.e. frames already received may be  
read out.  
A SFLUSHRXcommand strobe is required after  
a RXFIFO overflow to enable reception of new  
data.  
RFSTATUS.FIFO  
bit  
low  
while  
the  
RFSTATUS.FIFOP bit is high. Data already in  
CC2430 Data Sheet (rev. 2.1) SWRS036F  
Page 158 of 211