CC2430
Radio : FIFO access
RFIM (0x91) – RF Interrupt Mask
Bit
Name
Reset
R/W
Description
7
0
R/W
Voltage regulator for radio has been turned on
IM_RREG_PD
0
1
Interrupt disabled
Interrupt enabled
6
5
0
0
R/W
R/W
TX completed with packet sent. Also for acknowledge frames if RF
register IRQSRC.TXACK is 1
IM_TXDONE
IM_FIFOP
0
1
Interrupt disabled
Interrupt enabled
Number of bytes in RXFIFO is above threshold set by
IOCFG0.FIFOP_THR
0
1
Interrupt disabled
Interrupt enabled
4
3
2
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Start of frame delimiter (SFD) has been detected
IM_SFD
0
1
Interrupt disabled
Interrupt enabled
Clear channel assessment (CCA) indicates that channel is clear
IM_CCA
0
1
Interrupt disabled
Interrupt enabled
CSMA-CA/strobe processor (CSP) wait condition is true
IM_CSP_WT
IM_CSP_STOP
IM_CSP_INT
0
1
Interrupt disabled
Interrupt enabled
CSMA-CA/strobe processor (CSP) program execution stopped
0
1
Interrupt disabled
Interrupt enabled
CSMA-CA/strobe processor (CSP) INT instruction executed
0
1
Interrupt disabled
Interrupt enabled
14.5 FIFO access
The TXFIFO and RXFIFO may be accessed
RFSTATUS.FIFOand RFSTATUS.FIFOPonly
through the SFR register RFD(0xD9).
apply to the RXFIFO.
Data is written to the TXFIFO when writing to
the RFD register. Data is read from the he
RXFIFO when the RFDregister is read.
The TXFIFO may be flushed by issuing a
SFLUSHTX command strobe. Similarly, a
SFLUSHRX command strobe will flush the
receive FIFO.
The RF register bits RFSTATUS.FIFO and
RFSTATUS.FIFOP provide information on the
data in the receive FIFO, as described in
section 14.6 on page 157. Note that the
The FIFO may contain 256 bytes (128 bytes
for RX and 128 bytes for TX).
RFD (0xD9) – RF Data
Bit
Name
Reset R/W
Description
RFD[7:0]
0x00 R/W
7:0
Data written to the register is written to the
TXFIFO. When reading this register, data from the
RXFIFO is read
14.6 DMA
It is possible, and in most cases
recommended, to use direct memory access
(DMA) to move data between memory and the
radio. The DMA controller is described in
section 13.5. Refer to this section for a
detailed description on how to setup and use
DMA transfers.
To support the DMA controller there is one
DMA trigger associated with the radio, this is
the RADIO DMA trigger (DMA trigger 19). The
RADIO DMA trigger is activated by two events.
The first event to cause a RADIO DMA trigger,
is when the first data is present in the RXFIFO,
i.e. when the RXFIFO goes from the empty
state to the non-empty state. The second
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 157 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
