CC2430
Peripherals
The receiver will check both stop bits when
UxUCR.SPB is set. Note that the RX interrupt
will be set when first stop bit is checked OK. If
second stop bit is not OK there will be a delay
: USART
in when the framing error bit, UxCSR.FE, is
set. This delay is baud rate dependable (bit
duration).
13.14.2 SPI Mode
This section describes the SPI mode of
operation for synchronous communication. In
SPI mode, the USART communicates with an
external system through a 3-wire or 4-wire
interface. The interface consists of the pins
MOSI, MISO, SCK and SS_N. Refer to section
13.1 for description of how the USART pins
are assigned to the I/O pins.
•
•
•
•
3-wire (master) and 4-wire SPI interface
Master and slave modes
Configurable SCK polarity and phase
Configurable LSB or MSB first transfer
The SPI mode is selected when UxCSR.MODE
is set to 0.
In SPI mode, the USART can be configured to
operate either as an SPI master or as an SPI
slave by writing the UxCSR.SLAVEbit.
The SPI mode includes the following features:
13.14.2.1
SPI Master Operation
An SPI byte transfer in master mode is
initiated when the UxDBUF register is written.
The USART generates the SCK serial clock
using the baud rate generator (see section
13.14.4) and shifts the provided byte from the
transmit register onto the MOSI output. At the
same time the receive register shifts in the
received byte from the MISO input pin.
transmission has been initiated. Note that data
should not be written to UxDBUF until
UxCSR.TX_BYTE is 1. For DMA transfers this
is handled automatically. For back-to-back
transmits using DMA the UxGDR.CPHA bit
must be set to zero, if not transmitted bytes
can become corrupted. For systems requiring
setting
of
UxGDR.CPHA,
polling
UxCSR.TX_BYTE is needed.
The UxCSR.ACTIVE bit goes high when the
transfer starts and low when the transfer ends.
When the transfer ends, the UxCSR.TX_BYTE
bit is set to 1.
Also note the difference between transmit
interrupt and receive interrupt as the former
arrives approximately 8 bit periodes prior to
the latter.
The polarity and clock phase of the serial clock
SCK is selected by UxGCR.CPOL and
UxGCR.CPHA. The order of the byte transfer is
selected by the UxGCR.ORDERbit.
SPI master mode operation as described
above is a 3-wire interface. No select input is
used to enable the master. If the external
slave requires a slave select signal this can be
implemented through software using
general-purpose I/O pin.
At the end of the transfer, the received data
byte is available for reading from the UxDBUF.
A receive interrupt is generated when this new
data is ready in the UxDBUF USART
Receive/Transmit Data register.
a
A transmit interrupt is generated when the unit
is ready to accept another data byte for
transmission. Since UxDBUF is double-
buffered, this happens just after the
13.14.2.2
SPI Slave Operation
An SPI byte transfer in slave mode is
controlled by the external system. The data on
the MOSI input is shifted into the receive
register controlled by the serial clock SCK
which is an input in slave mode. At the same
time the byte in the transmit register is shifted
out onto the MISO output.
Then the UxCSR.RX_BYTE bit is set and a
receive interrupt is generated.
The expected polarity and clock phase of SCK
is
selected
by UxGCR.CPOL
and
UxGCR.CPHA. The expected order of the byte
transfer is selected by the UxGCR.ORDERbit.
The UxCSR.ACTIVE bit goes high when the
transfer starts and low when the transfer ends.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 144 of 211
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