CC2430
Peripherals
serial
: USART
13.14 USART
USART0 and
USART1
are
two USARTs have identical function, and are
assigned to separate I/O pins. Refer to section
13.1 for I/O configuration.
communications interfaces that can be
operated separately in either asynchronous
UART mode or in synchronous SPI mode. The
13.14.1 UART mode
For asynchronous serial interfaces, the UART
mode is provided. In the UART mode the
interface uses a two-wire or four-wire interface
consisting of the pins RXD, TXD and optionally
RTS and CTS. The UART mode of operation
includes the following features:
The UART mode provides full duplex
asynchronous
transfers,
and
the
synchronization of bits in the receiver does not
interfere with the transmit function. A UART
byte transfer consists of a start bit, eight data
bits, an optional ninth data or parity bit, and
one or two stop bits. Note that the data
transferred is referred to as a byte, although
the data can actually consist of eight or nine
bits.
•
•
•
•
•
8 or 9 data bits
Odd, even or no parity
Configurable start and stop bit level
Configurable LSB or MSB first transfer
Independent
interrupts
The UART operation is controlled by the
USART Control and Status registers, UxCSR
and the UART Control register UxUCRwhere x
is the USART number, 0 or 1.
receive
and
transmit
•
•
Independent receive and transmit DMA
triggers
Parity and framing error status
The UART mode is selected when
UxCSR.MODEis set to 1.
13.14.1.1
UART Transmit
A UART transmission is initiated when the
USART Receive/transmit Data Buffer, UxDBUF
register is written. The byte is transmitted on
TXDx output pin. The UxDBUF register is
double-buffered.
When
the
transmission
ends,
the
UxCSR.TX_BYTE bit is set to 1. An interrupt
request is generated when the UxDBUF
register is ready to accept new transmit data.
This
happens
immediately
after
the
transmission has been started, hence a new
data byte value can be loaded into the data
buffer while the byte is being transmitted.
The UxCSR.ACTIVE bit goes high when the
byte transmission starts and low when it ends.
13.14.1.2
UART Receive
Data reception on the UART is initiated when
a 1 is written to the UxCSR.REbit. The UART
will then search for a valid start bit on the
RXDx input pin and set the UxCSR.ACTIVEbit
high. When a valid start bit has been detected
the received byte is shifted into the receive
register. The UxCSR.RX_BYTEbit is set and a
receive interrupt is generated when the
operation has completed. At the same time
UxCSR.ACTIVEwill go low.
The received data byte is available through the
UxDBUF register. When UxDBUF is read,
UxCSR.RX_BYTEis cleared by hardware.
13.14.1.3
UART Hardware Flow Control
Hardware flow control is enabled when the
UxUCR.FLOW bit is set to 1. The RTS output
will then be driven low when the receive
register is empty and reception is enabled.
Transmission of a byte will not occur before
the CTS input go low.
13.14.1.4
UART Character Format
The number of stop bits to be transmitted is
set to one or two bits determined by the
register bit UxUCR.SPB. The receiver will
always check for one stop bit. If the first stop
bit received during reception is not at the
expected stop bit level, a framing error is
signaled by setting register bit UxCSR.FEhigh.
UxCSR.FE is cleared when UxCSR is read.
If the BIT9and PARITYbits in register UxUCR
are set high, parity generation and detection is
enabled. The parity is computed and
transmitted as the ninth bit, and during
reception, the parity is computed and
compared to the received ninth bit. If there is a
parity error, the UxCSR.ERR bit is set high.
This bit is cleared when UxCSRis read.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 143 of 211
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