CC2430
Peripherals : Watchdog Timer
13.13 Watchdog Timer
The watchdog timer (WDT) is intended as a
recovery method in situations where the CPU
may be subjected to a software upset. The
WDT shall reset the system when software
fails to clear the WDT within a selected time
interval. The watchdog can be used in
applications that are subject to electrical noise,
power glitches, electrostatic discharge etc., or
where high reliability is required. If the
watchdog function is not needed in an
application, it is possible to configure the
watchdog timer to be used as an interval timer
that can be used to generate interrupts at
selected time intervals.
•
•
•
•
•
Four selectable timer intervals
Watchdog mode
Timer mode
Interrupt request generation in timer mode
Clock independent from system clock
The WDT is configured as either a watchdog
timer or as a timer for general-purpose use.
The operation of the WDT module is controlled
by the WDCTL register. The watchdog timer
consists of an 15-bit counter clocked by the
32.768 kHz clock. Note that the contents of the
15-bit counter is not user-accessible. The
contents of the 15-bit counter is reset to
0x0000 when power modes PM2 or PM3 is
entered.
The features of the watchdog timer are as
follows:
13.13.1 Watchdog mode
The watchdog timer is disabled after a system
reset. To set the WDT in watchdog mode the
WDCTL.MODE bit is set to 0. The watchdog
timer counter starts incrementing when the
enable bit WDCTL.EN is set to 1. When the
timer is enabled in watchdog mode it is not
possible to disable the timer. Therefore, writing
a 0 to WDCTL.EN has no effect if a 1 was
already written to this bit when WDCTL.MODE
was 0.
incrementing its value. The watchdog clear
sequence consists of writing 0xA to
WDCTL.CLR[3:0] followed by writing 0x5 to
the same register bits within one half of a
watchdog clock period. If this complete
sequence is not performed, the watchdog
timer generates a reset signal for the system.
Note that as long as a correct watchdog clear
sequence begins within the selected timer
interval, the counter is reset when the
complete sequence has been received.
The WDT operates with a watchdog timer
clock frequency of 32.768 kHz. This clock
frequency gives time-out periods equal to 1.9
ms, 15.625 ms, 0.25 s and 1 s corresponding
to the count value settings 64, 512, 8192 and
32768 respectively.
When the watchdog timer has been enabled in
watchdog mode, it is not possible to change
the mode by writing to the WDCTL.MODE bit.
The timer interval value can be changed by
writing to the WDCTL.INT[1:0]bits.
Note that it is recommended that user software
clears the watchdog timer at the same time as
the timer interval value is changed, in order to
avoid an unwanted watchdog reset.
If the counter reaches the selected timer
interval value, the watchdog timer generates a
reset signal for the system. If a watchdog clear
sequence is performed before the counter
reaches the selected timer interval value, the
counter is reset to 0x0000 and continues
In watchdog mode, the WDT does not produce
an interrupt request.
13.13.2 Timer mode
To set the WDT in normal timer mode, the
WDCTL.MODE bit is set to 1. When register bit
WDCTL.ENis set to 1, the timer is started and
the counter starts incrementing. When the
counter reaches the selected interval value,
the timer will produce an interrupt request.
When the timer is cleared the contents of the
counter is set to 0x0000. Writing a 0 to the
enable bit WDCTL.EN stops the timer and
writing 1 restarts the timer from 0x0000.
The
timer
interval
is
set
by
the
WDCTL.INT[1:0]bits. In timer mode, a reset
will not be produced when the timer interval
has been reached.
In timer mode, it is possible to clear the timer
contents by writing a 1 to WDCTL.CLR[0].
13.13.3 Watchdog and Power Modes
In the two lowest power modes, PM2 and
PM3, the watchdog is disabled and reset. After
wake up it will still be enabled and configured
as it was prior to entering PM2/3 mode, but
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 141 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
