CC2430
Peripherals
: MAC Timer (Timer2)
T2THD (0xA7) – Timer 2 Timer Value High Byte
Bit
Name
Reset
R/W
Description
7:0
THD[7:0]
0x00
R/W
The value read from this register is the high-order byte of the timer
value. The high-order byte read is from timer value at the last instant
when T2TLDwas read.
The value written to this register while the timer is running is the high-
order byte of the timer delta counter value. The low-order byte of this
value is the value last written to T2TLD. The timer will halt for delta
clock cycles.
The value written to this register while the timer is idle will be written to
the high-order byte of the timer.
T2TLD (0xA6) – Timer 2 Timer Value Low Byte
Bit
Name
Reset
R/W
Description
7:0
TLD[7:0]
0x00
R/W
The value read from this register is the low-order byte of the timer value.
The value written to this register while the timer is running is the low-
order byte of the timer delta counter value. The timer will halt for delta
clock cycles. The value written to T2TLDwill not take effect until T2THD
is written.
The value written to this register while the timer is idle will be written to
the low-order byte of the timer.
T2CMP (0x94) – Timer 2 Compare Value
Bit
Name
Reset
R/W
Description
CMP[7:0]
0x00
R/W
7:0
Timer Compare value. A timer compare occurs when the compare
source selected by T2CNF.CMSELequals the value held in CMP
.
T2OF2 (0xA3) – Timer 2 Overflow Count 2
Bit
Name
Reset
R/W
Description
-
0000
R0
7:4
3:0
Not used, read as 0
OF2[3:0]
0x00
R/W
Overflow count. High bits T2OF[19:16]. T2OFis incremented by 1
each time the timer overflows i.e. timer counts to a value greater or
equal to period. When reading this register, the value read is the value
latched when T2OF0was read. Writing to this register when the timer is
in IDLE or RUN states will force the overflow count to be set to the
value written to T2OF2:T2OF1:T2OF0.If the count would otherwise be
incremented by 1 when this register is written then 1 is added to the
value written.
T2OF1 (0xA2) – Timer 2 Overflow Count 1
Bit
Name
Reset
R/W
Description
OF1[7:0]
0x00
R/W
Overflow count. Middle bits T2OF[15:8]. T2OF is incremented by 1 each
time the timer overflows i.e. timer counts to a value greater or equal to
period. When reading this register, the value read is the value latched
when T2OF0 was read. Writing to this register when the timer is in IDLE
or RUN states will force the overflow count to be set to the value written
to T2OF2:T2OF1:T2OF0. If the count would otherwise be incremented
by 1 when this register is written then 1 is added to the value written.
The value written will not take effect until T2OF2 is written.
7:0
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 114 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
