CC2430
Peripherals
:
MAC Timer (Timer2)
when using Timer2 in PM1 or PM2.
T2CAPHPH and T2CAPHPL should be avoided
13.7.5
Timer 2 Registers
The SFR registers associated with Timer 2 are
listed in this section. These registers are the
following:
• T2OF0– Timer 2 Overflow Count 0
• T2CAPHPH– Timer 2 Capture/Period High
• T2CAPLPL– Timer 2 Capture/Period Low
• T2PEROF2
Capture/Compare 2
• T2PEROF1
Capture/Compare 1
• T2PEROF0
–
Timer
2
2
2
Overflow
Overflow
Overflow
• T2CNF– Timer 2 Configuration
• T2HD– Timer 2 Count/Delta High
• T2LD– Timer 2 Count/Delta Low
• T2CMP– Timer 2 Compare
• T2OF2– Timer 2 Overflow Count 2
• T2OF1– Timer 2 Overflow Count 1
–
Timer
–
Timer
Capture/Compare 0
T2CNF (0xC3) – Timer 2 Configuration
Bit
Name
Reset
R/W
Description
7
CMPIF
0
R/W0
Timer compare interrupt flag. This bit is set to 1 when a timer compare
event occurs. Cleared by software only. Writing a 1 to this bit has no
effect.
6
5
PERIF
0
0
R/W0
R/W0
Overflow interrupt flag. This bit is set to 1 when a period event occurs.
Cleared by software only. Writing a 1 to this bit has no effect.
OFCMPIF
Overflow compare interrupt flag. This bit is set to 1 when a overflow
compare occurs. Cleared by software only. Writing a 1 to this bit has no
effect.
4
3
-
0
0
R0
Not used. Read as 0
CMSEL
R/W
Timer compare source select.
0
1
Compare with 16-bit Timer bits [15:8]
Compare with 16-bit Timer bits [7:0]
2
1
-
0
1
R/W
R/W
Reserved. Always set to 0
SYNC
Enable synchronized start and stop.
0 start and stop of timer is immediate
1 start and stop of timer is synchronized with 32.768 kHz edge and new
timer values are reloaded.
0
RUN
0
R/W
Dual function: timer start / timer status.
Writing this bit will start or stop the timer.
0 stop timer
1 start timer
Reading this bit the current state of the timer is returned.
0 timer is stopped (IDLE state)
1 timer is running (RUN state)
Note when SYNC=1 (the reset condition), the timer status does not
change immediately when the timer is started or stopped. Instead the
timer status is changed when the actual synchronous start/stop takes
place. Prior to the synchronous start/stop event, the read value of RUN
will differ from the last value written.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 113 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
