CC1110Fx / CC1111Fx
Component
Value at 315MHz
Value at 433MHz
Value at
Manufacturer
868/915MHz
C301
1 µF ± 10%, 0402 X5R
Murata GRM1555C series
Murata GRM1555C series
C201/C211
C203/C214
27 pF ± 5%, 0402 NP0
33pF pF ± 5%,
0402 NP0
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
C121
C122
C123
C124
C125
C131
6.8 pF ± 0.5 pF,
0402 NP0
3.9 pF ± 0.25 pF,
0402 NP0
1.0 pF ± 0.25 pF,
0402 NP0
12 pF ± 5%, 0402
NP0
8.2 pF ± 0.5 pF,
0402 NP0
1.5 pF ± 0.25 pF,
0402 NP0
6.8 pF ± 0.5 pF,
0402 NP0
5.6 pF ± 0.5 pF,
0402 NP0
3.3 pF ± 0.25 pF,
0402 NP0
220 pF ± 5%,
0402 NP0
220 pF ± 5%,
0402 NP0
100 pF ± 5%, 0402
NP0
220 pF ± 5%,
0402 NP0
220 pF ± 5%,
0402 NP0
100 pF ± 5%, 0402
NP0
6.8 pF ± 0.5 pF,
0402 NP0
3.9 pF ± 0.25 pF,
0402 NP0
1.5 pF ± 0.25 pF,
0402 NP0
C171/C181
L121
15pF ± 5%, 0402 NP0
Murata GRM1555C series
Murata LQG15HS series
33 nH ± 5%, 0402
monolithic
27 nH ± 5%, 0402
monolithic
12 nH ± 5%, 0402
monolithic
L122
L123
L124
L131
L132
18 nH ± 5%, 0402
monolithic
22 nH ± 5%, 0402
monolithic
18 nH ± 5%, 0402
monolithic
Murata LQG15HS series
Murata LQG15HS series
Murata LQG15HS series
Murata LQG15HS series
Murata LQG15HS series
33 nH ± 5%, 0402
monolithic
27 nH ± 5%, 0402
monolithic
12 nH ± 5%, 0402
monolithic
12 nH ± 5%, 0402
monolithic
33 nH ± 5%, 0402
monolithic
27 nH ± 5%, 0402
monolithic
12 nH ± 5%, 0402
monolithic
18 nH ± 5%, 0402
monolithic
R262/R263
R264
R271
X1
33 kΩ ± 2%, 0402
1.5 kΩ ± 1%, 0402
56 kΩ ± 1%, 0402
Koa RK73 series
NDK, AT-41CD2
26.0 MHz surface mount crystal
32.768 kHz surface mount crystal (optional)
48 MHz surface mount crystal
X2
X3
Table 29: Bill of Materials for the CC1110Fx/CC1111Fx Application Circuits
10.6 PCB Layout Recommendations
The top layer should be used for signal routing,
and the open areas should be filled with
metallization connected to ground using
several vias.
component side of the PCB to avoid migration
of solder through the vias during the solder
reflow process.
The solder paste coverage should not be
100%. If it is, out gassing may occur during the
reflow process, which may cause defects
(splattering, solder balling). Using “tented” vias
reduces the solder paste coverage below
100%.
The area under the chip is used for grounding
and shall be connected to the bottom ground
plane with several vias for good thermal
performance. In the CC1110EM reference
designs [1] 9 vias are placed inside the
exposed die attached pad. These vias should
be “tented” (covered with solder mask) on the
See Figure 13 for top solder resist and top
paste masks.
SWRS033E
Page 40 of 239
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