CC1110Fx / CC1111Fx
Each decoupling capacitor should be placed
as close as possible to the supply pin it is
supposed to decouple. Each decoupling
capacitor should be connected to the power
line (or power plane) by separate vias. The
best routing is from the power line (or power
plane) to the decoupling capacitor and then to
the CC1110Fx supply pin. Supply power filtering
is very important.
coupling and should be avoided unless
absolutely necessary.
The external components should ideally be as
small as possible (0402 is recommended) and
surface
mount
devices
are
highly
recommended. Please note that components
smaller than those specified may have differing
characteristics.
Schematic, BOM, and layout Gerber files are
all available from the TI website for both the
CC1110EM reference designs [1], [2], [3] and
the CC1111 USB Dongle reference design [4].
Each decoupling capacitor ground pad should
be connected to the ground plane using a
separate via. Direct connections between
neighboring power pins will increase noise
Figure 13: Left: Top Solder Resist Mask (negative). Right: Top Paste Mask. Circles are Vias.
11 8051 CPU
This section describes the 8051 CPU core,
with interrupts, memory, and instruction set.
11.1 8051 Introduction
The CC1110Fx/CC1111Fx includes an 8-bit CPU
core which is an enhanced version of the
industry standard 8051 core.
• A second data pointer
• Extended 18-source interrupt unit
The 8051 core is object code compatible with
the industry standard 8051 microcontroller.
That is, object code compiled with an industry
standard 8051 compiler or assembler
executes on the 8051 core and is functionally
equivalent. However, because the 8051 core
uses a different instruction-timing than many
other 8051 variants, existing code with timing
loops may require modification. Also because
the peripheral units such as timers and serial
ports differ from those on other 8051 cores,
code which includes instructions using the
peripheral units SFRs will not work correctly.
The enhanced 8051 core uses the standard
8051 instruction set. Instructions execute
faster than the standard 8051 due to the
following:
• One clock per instruction cycle is used
as opposed to 12 clocks per instruction
cycle in the standard 8051.
• Wasted bus states are eliminated.
Since an instruction cycle is aligned with
memory fetch when possible, most of the
single byte instructions are performed in a
single clock cycle. In addition to the speed
improvement, the enhanced 8051 core also
includes architectural enhancements:
SWRS033E
Page 41 of 239
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