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CC1110FX 参数 Datasheet PDF下载

CC1110FX图片预览
型号: CC1110FX
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗低于1 GHz的射频系统级芯片(SoC )与MCU,存储器,收发器和USB控制器 [Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller]
分类和应用: 存储射频控制器
文件页数/大小: 240 页 / 2823 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC1110Fx / CC1111Fx  
Register  
Name  
SFR  
Address  
Module  
Description  
Retention5  
U0GCR  
U1CSR  
U1DBUF  
U1BAUD  
U1UCR  
U1GCR  
ENDIAN  
WDCTL  
0xC5  
0xF8  
0xF9  
0xFA  
0xFB  
0xFC  
0x95  
0xC9  
USART0  
USART1  
USART1  
USART1  
USART1  
USART1  
MEMORY  
WDT  
USART 0 Generic Control  
Y
Y
USART 1 Control and Status  
USART 1 Receive/Transmit Data Buffer  
USART 1 Baud Rate Control  
USART 1 UART Control  
Y
Y
Y,[7]N  
USART 1 Generic Control  
Y
Y
Y
USB Endianess Control (CC1111Fx)  
Watchdog Timer Control  
Table 31: CC1110Fx/CC1111Fx Specific SFR Overview  
11.2.3.4 Radio Registers  
space and reside in address range 0xDF00 -  
0xDF3D.  
The radio registers are all related to Radio  
configuration and control. The RF registers can  
only be accessed through XDATA memory  
Table 32 gives a descriptive overview of these  
registers. Each register is described in detail in  
section 14.19, starting on page 208.  
XDATA  
Register  
Description  
Retention6  
Address  
0xDF00  
0xDF01  
0xDF02  
0xDF03  
0xDF04  
0xDF05  
0xDF06  
0xDF07  
0xDF08  
0xDF09  
0xDF0A  
0xDF0B  
0xDF0C  
0xDF0D  
0xDF0E  
0xDF0F  
0xDF10  
0xDF11  
0xDF12  
0xDF13  
0xDF14  
0xDF15  
0xDF16  
SYNC1  
Sync word, high byte  
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SYNC0  
Sync word, low byte  
PKTLEN  
PKTCTRL1  
PKTCTRL0  
ADDR  
Packet length  
Packet automation control  
Packet automation control  
Device address  
CHANNR  
FSCTRL1  
FSCTRL0  
FREQ2  
Channel number  
Frequency synthesizer control  
Frequency synthesizer control  
Frequency control word, high byte  
Frequency control word, middle byte  
Frequency control word, low byte  
Modem configuration  
FREQ1  
FREQ0  
MDMCFG4  
MDMCFG3  
MDMCFG2  
MDMCFG1  
MDMCFG0  
DEVIATN  
MCSM2  
Modem configuration  
Modem configuration  
Modem configuration  
Modem configuration  
Modem deviation setting  
Main Radio Control State Machine configuration  
Main Radio Control State Machine configuration  
Main Radio Control State Machine configuration  
Frequency Offset Compensation configuration  
Bit Synchronization configuration  
Y
Y
Y
Y
Y
MCSM1  
MCSM0  
FOCCFG  
BSCFG  
6
Registers without retention are in their reset state after PM2 or PM3. This is only applicable for  
registers / bits that are defined as R/W  
SWRS033E  
Page 50 of 239  
 
 
 
 
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