CC1110Fx / CC1111Fx
Unlike on a standard 8051, the SFRs are also
accessible through the XDATA and CODE
memory space at the address range 0xDF80 -
0xDFFF.
• The USB registers are mapped into the
address range 0xDE00 - 0xDE3F on the
CC1111Fx, but are not implemented on the
CC1110Fx.
Some CPU-specific SFRs reside inside the
CPU core and can only be accessed using the
SFR memory space and not through the
duplicate mapping into XDATA/CODE memory
space. These registers are shown in gray in
Table 30. Be aware that these registers can
not be accessed using DMA.
This memory mapping allows the DMA
controller (and the CPU) access to all the
physical memories in a single unified address
space.
Be aware that access to unimplemented areas
in the unified memory space will give an
undefined result.
11.2.3 Physical Memory
11.2.3.1 SRAM
11.2.2.2 CODE Memory Space
On a standard 8051 this memory space would
hold the program memory, where the MCU
reads the program/instructions.
The CC1110Fx/CC1111Fx contains static RAM. At
power-on the contents of RAM is undefined.
The RAM size is 1, 2, or 4 KB in total, mapped
to the memory range 0xF000 – 0xFFFF. In the
F8 version, memory range 0xF300 - 0xFEFF is
unimplemented while on the F16 version,
All memory spaces are mapped into the CODE
memory space and the mapping is identical to
the XDATA memory space, hence the
CC1110Fx/CC1111Fx has what can be referred to
as a unified memory space.
memory range 0xF700
unimplemented.
–
0xFEFF is
Due to this, the CC1110Fx/CC1111Fx allows
execution of a program stored in SRAM. This
allows the program to be easily updated
without writing to flash (which have a limited
erase/write cycles) This is particularly useful
on the CC1111Fx, where parts of the firmware
can be downloaded from the windows USB
driver.
The memory locations 0xFDA2 - 0xFEFF on
F32 version consist of 350 bytes in unified
memory space that do not retain data when
power modes PM2 or PM3 is entered. All other
RAM memory locations are retained in all
power modes.
11.2.3.2 Flash Memory
Executing a program from SRAM instead of
flash will also result in a lower power
consumption and may be interesting for battery
powered devices.
The on-chip flash memory consists of 8192,
16384, or 32768 bytes (F8, F16, and F32). The
flash memory is primarily intended to hold
program code. The flash memory has the
following features:
11.2.2.3 DATA Memory Space
• Flash page erase time: 20 ms
• Flash chip (mass) erase time: 200 ms
• Flash write time (2 bytes): 20 µs
• Data retention (at room temperature):
100 years
The 8-bit address range of DATA memory
space is mapped into address 0xFF00 –
0xFFFF and is accessible through the unified
memory space. Just like on a standard 8051,
the upper 128 byte share address with the
SFR and can only be accessed indirectly, the
stack is normally located here. The lower 48
bytes are reserved, and hold 4 register banks
used by the MCU. The 16 bytes on addresses
0x20 to 0x2F are bit addressable.
• Program/erase endurance: Minimum
1,000 cycles
The flash memory consists of the Flash Main
Pages (up to 32 times 1 KB) which is where
the CPU reads program code and data. The
The DATA memory will retain its contents in all
four power modes.
flash memory also contains
a
Flash
Information Page (1 KB) which contains the
Flash Lock Bits. The lock protect bits are
written as a normal flash write to FWDATA but
the Debug Interface needs to select the Flash
Information Page first instead of the Flash
Main Page. The Information Page is selected
through the Debug Configuration which is
written through the Debug Interface only. The
Flash Controller (see section 13.3) is used to
11.2.2.4 SFR Memory Space
The SFR memory space is identical to a
standard 8051.
The 128 hardware SFRs are accessed through
this memory space.
SWRS033E
Page 46 of 239
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