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CC1110FX 参数 Datasheet PDF下载

CC1110FX图片预览
型号: CC1110FX
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗低于1 GHz的射频系统级芯片(SoC )与MCU,存储器,收发器和USB控制器 [Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller]
分类和应用: 存储射频控制器
文件页数/大小: 240 页 / 2823 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC1110Fx / CC1111Fx  
11.2 Memory  
The 8051 CPU architecture has four different  
memory spaces. The 8051 has separate  
memory spaces for program memory and data  
memory. The 8051 memory spaces are the  
following (see section 11.2.1 and 11.2.2 for  
details):  
DMA transfers and hardware debugger  
operation.  
How the different memory spaces are mapped  
onto the three physical memories (8/16/32 KB  
flash program memory, 1/2/48 KB SRAM, and  
hardware registers (SFR, radio, I2S, and USB  
(CC1111Fx)) is described in sections 11.2.1 and  
11.2.2.  
CODE. A 16-bit read-only memory space for  
program memory.  
DATA. An 8-bit read/write data memory  
space, which can be directly or indirectly,  
accessed by a single cycle CPU instruction,  
thus allowing fast access. The lower 128 bytes  
of the DATA memory space can be addressed  
either directly or indirectly, the upper 128 bytes  
only indirectly.  
11.2.1 Memory Map  
This section gives an overview of the memory  
map.  
Both the DATA and the SFR memory space is  
mapped to the XDATA and CODE memory  
space as shown in Figure 14, Figure 15, and  
Figure 16 (the CODE and XDATA memory  
spaces are mapped identically), and  
CC1110FX/CC1111FX has what can be called a  
unified memory space.  
XDATA. A 16-bit read/write data memory  
space, which usually requires 4 - 5 CPU  
instruction cycles to access, thus giving slow  
access. XDATA assesses is also slower in  
hardware than DATA accesses as the CODE  
and XDATA memory spaces share a common  
bus on the CPU core (instruction pre-fetch  
from CODE can not be performed in parallel  
with XDATA accesses).  
Mapping all the memory spaces to XDATA  
allows the DMA controller access to all  
physical memory and thus allows DMA  
transfers between the different 8051 memory  
spaces. This also means that any instruction  
that read, write, or manipulate an XDATA  
variable can be used on the entire unified  
memory space, except writing to or changing  
data in flash.  
SFR. A 7-bit read/write register memory  
space, which can be directly accessed by a  
single CPU instruction. For SFRs whose  
address is divisible by eight, each bit is also  
individually addressable.  
Mapping all memory spaces to the CODE  
memory space is primarily done to allow  
program execution out of the SRAM/XDATA.  
The four different memory spaces are distinct  
in the 8051 architecture, but are partly  
overlapping in the CC1110Fx/CC1111Fx to ease  
SWRS033E  
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