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CC1110FX 参数 Datasheet PDF下载

CC1110FX图片预览
型号: CC1110FX
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗低于1 GHz的射频系统级芯片(SoC )与MCU,存储器,收发器和USB控制器 [Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller]
分类和应用: 存储射频控制器
文件页数/大小: 240 页 / 2823 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC1110Fx / CC1111Fx  
7.9 Analog Temperature Sensor  
TA= 25 °C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the  
CC1110EM reference designs ([1]).  
Parameter  
Min  
Typ  
Max  
Unit  
Condition/Note  
0.660  
0.755  
0.859  
0.958  
2.54  
0
V
V
V
V
Output voltage at -40 °C  
Output voltage at 0 °C  
Output voltage at +40 °C  
Output voltage at +80 °C  
Temperature coefficient  
mV/°C Fitted from -20 °C to +80 °C  
Error in calculated  
temperature, calibrated  
-2 *  
2 *  
°C  
From –20°C to +80°C when using 2.43 mV / °C, after 1-point  
calibration at room temperature  
* The indicated minimum and maximum error with 1-point  
calibration is based on measured values for typical process  
parameters  
Current consumption  
0.3  
mA  
increase when enabled  
Table 17: Analog Temperature Sensor Parameters  
7.10 7-12 bit ADC  
TA = 25 °C, VDD = 3.0V if nothing else stated. The numbers given here are based on tests performed  
in accordance with IEEE Std 1241-2000 [8]. The ADC data are from CC2430 characterization. As the  
CC1110Fx/C1111Fx uses the same ADC, the numbers listed in Table 18 should be good indicators of the  
performance to be expected from CC1110Fx and CC1111Fx. Note that these numbers will apply for 24  
MHz operated systems (like CC1110Fx using a 24 MHz crystal or CC1111Fx using a 48 MHz crystal).  
Performance will be slightly different for other crystal frequencies (e.g. 26 MHz and 27 MHz).  
Parameter  
Min  
Typ  
Max  
Unit Condition/Note  
Input voltage  
0
0
0
VDD  
VDD  
VDD  
V
V
V
VDD is voltage on AVDD pin (2.0 – 3.6 V)  
External reference voltage  
VDD is voltage on AVDD pin (2.0 – 3.6 V)  
VDD is voltage on AVDD pin (2.0 – 3.6 V)  
External reference voltage  
differential  
Input resistance, signal  
197  
Simulated using 4 MHz clock speed (see section  
13.10.2.7)  
kΩ  
Full-Scale Signal4  
ENOB4  
2.97  
5.7  
V
Peak-to-peak, defines 0 dBFS  
7-bits setting  
bits  
Single ended input  
7.5  
9-bits setting  
9.3  
10-bits setting  
10.8  
6.5  
12-bits setting  
ENOB4  
bits  
7-bits setting  
Differential input  
8.3  
9-bits setting  
10.0  
11.5  
0-20  
10-bits setting  
12-bits setting  
Useful Power Bandwidth  
THD4  
kHz  
7-bits setting, both single and differential  
-Single ended input  
-Differential input  
-75.2  
-86.6  
dB  
dB  
12-bits setting, -6 dBFS  
12-bits setting, -6 dBFS  
4 Measured with 300 Hz Sine input and VDD as reference.  
SWRS033E  
Page 23 of 239  
 
 
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