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CC1110FX 参数 Datasheet PDF下载

CC1110FX图片预览
型号: CC1110FX
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗低于1 GHz的射频系统级芯片(SoC )与MCU,存储器,收发器和USB控制器 [Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller]
分类和应用: 存储射频控制器
文件页数/大小: 240 页 / 2823 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC1110Fx / CC1111Fx  
7.13 Debug Interface AC Characteristics  
TA = 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the  
CC1110EM reference designs ([1]).  
Parameter  
Min  
Typ  
Max  
Unit  
Condition/Note  
Debug clock  
period  
125  
ns  
See item 1, Figure 6  
Note: CLKCON.CLKSPDmust be 000 or 001 when using  
the debug interface  
Debug data setup  
Debug data hold  
5
5
ns  
ns  
ns  
See item 2, Figure 6  
See item 3, Figure 6  
Clock to data  
delay  
10  
See item 4, Figure 6, load = 10 pF  
RESET_N inactive  
after P2_2 rising  
10  
ns  
See item , Figure 6  
Table 21: Debug Interface AC Characteristics  
1
DEBUG CLK  
P2_2  
3
2
DEBUG DATA  
P2_1  
4
DEBUG DATA  
P2_1  
5
RESET_N  
Figure 6: Debug Interface AC Characteristics  
7.14 Port Outputs AC Characteristics  
TA = 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the  
CC1110EM reference designs ([1]).  
Parameter  
Min  
Typ  
Max  
Unit Condition/Note  
P0_[0:7], P1_[2:7],  
P2_[0:4] Port output  
rise time  
(PICTL.PADSC=0/  
PICTL.PADSC=1)  
3.15 /  
1.34  
ns  
Load = 10 pF  
Timing is with respect to 10% VDD and 90% VDD levels.  
Values are estimated  
P0_[0:7], P1_[2:7],  
3.2 /  
1.44  
ns  
Load = 10 pF  
P2_[0:4] Port output fall  
time (PICTL.PADSC=0  
/ PICTL.PADSC=1)  
Timing is with respect to 90% VDD and 10% VDD.  
Values are estimated  
Table 22: Port Outputs AC Characteristics  
SWRS033E  
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