SyncMOS Technologies International, Inc.
SM8958A
8-Bits Micro-controller
With 32KB flash & 1KB RAM embedded
Internal RAM Control Register (RCON, $85)
bit-7
Unused
Read / Write:
Reset value:
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
RAMS1
R/W
0
bit-0
RAMS0
R/W
0
SM8958A has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By instruction
MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1, RAMS0) of RCON. The
default setting of RAMS1, RAMS0 bits is 00 (page0).
RAMS1
0
0
1
RAMS0
0
1
0
MOVX @Ri i=0,1 mapping to expended RAM address
$0000 ~ $00FF
$0100 ~ $01FF
$0200 ~ $02FF
The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure.
System Control Register (SCONF, $BF)
bit-7
WDR
Read / Write:
Reset value:
R/W
0
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
OME
R/W
0
bit-0
ALEI
R/W
0
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow. WDR will be set to 1, The bit 7 (WDR) of
SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should
check WDR bit whenever un-predicted reset happened.
OME : 768 bytes on-chip RAM enable bit. The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 768 byte
RAM. The default setting of OME bit is 0 (disable).
ALEI : ALE output inhibit bit, to reduce EMI. Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output
to the ALE pin.
Specifications subject to change without notice contact your sales representatives for the most recent information.
8
Ver 2.1
SM8958A
08/2006
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
