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SM79108_06 参数 Datasheet PDF下载

SM79108_06图片预览
型号: SM79108_06
PDF下载: 下载PDF文件 查看货源
内容描述: 8 - 位微控制器,具有8KB闪存和256字节RAM的嵌入式 [8 - Bit Micro-controller with 8KB flash & 256 Bytes RAM embedded]
分类和应用: 闪存微控制器
文件页数/大小: 25 页 / 494 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SyncMOS Technologies International. Inc.  
SM79108  
Addr  
0E2H  
0E3H  
0E4H  
0E5H  
0E6H  
0E7H  
SFR  
Reset  
00H  
00H  
00H  
00H  
00H  
00H  
7
6
5
4
3
2
1
0
LCDB1  
LCDB2  
LCDB3  
LCDB4  
LCDB5  
LCDB6  
SEG2  
SEG4  
SEG6  
SEG8  
SEG10  
SEG12  
SEG2  
SEG4  
SEG6  
SEG8  
SEG10  
SEG12  
SEG2  
SEG4  
SEG6  
SEG8  
SEG10  
SEG12  
SEG2  
SEG4  
SEG6  
SEG8  
SEG10  
SEG12  
SEG3  
SEG5  
SEG7  
SEG9  
SEG11  
SEG13  
SEG3  
SEG5  
SEG7  
SEG9  
SEG11  
SEG13  
SEG3  
SEG5  
SEG7  
SEG9  
SEG11  
SEG13  
SEG3  
SEG5  
SEG7  
SEG9  
SEG11  
SEG13  
1. Watch Dog Timer  
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is  
useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead  
loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different  
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the  
WDT counter. User should check WDR bit of SCONF register whenever unpracticed reset happened  
The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway.  
There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is inde-  
pendent to the system frequency.  
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count  
with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when  
SM79108 been reset, either hardware reset or WDT reset.  
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of  
the 16-bit counter and let the counter re-start to count from the beginning.  
1.1 Watch Dog Timer Registers:  
Watch Dog Key Register - (WDTKEY, 97H)  
bit-7  
WDT  
KEY7  
W
bit-0  
WDT  
KEY0  
W
WDT  
KEY6  
W
WDT  
KEY5  
W
WDT  
KEY4  
W
WDT  
KEY3  
W
WDT  
KEY2  
W
WDT  
KEY1  
W
Read / Write:  
Reset value:  
0
0
0
0
0
0
0
0
By default, the WDTC is read only. User need to write values 1EH, 0E1H sequentially to the WDTKEY(97H) register to  
enable the WDTC write attribute, That is  
MOV WDTKEY, # 1EH  
MOV WDTKEY, # E1H  
When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY(97H) register to disable the  
WDTC write attribute, That is  
MOV WDTKEY, # E1H  
MOV WDTKEY, # 1EH  
Specifications subject to change without notice,contact your sales representatives for the most recent information.  
6/26  
Ver 2.1 SM79108 08/2006  
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